公开(公告)号：US20180350620A1

公开(公告)日：2018-12-06

申请号：US15987755

申请日：2018-05-23

Applicant: ASM IP Holding B.V.

Inventor： Masaru Zaitsu ,  Nobuyoshi Kobayashi ,  Akiko Kobayashi ,  Masaru Hori ,  Takayoshi Tsutsumi

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a carbon halide film using reactive species on the target layer on the substrate; and etching the carbon halide film using a plasma of a non-halogen hydrogen-containing etching gas, which plasma alone does not substantially etch the target layer, thereby generating a hydrogen halide as etchant species at a boundary region of the carbon halide film and the target layer, thereby etching a portion of the target layer in the boundary region.

公开(公告)号：US10115603B2

公开(公告)日：2018-10-30

申请号：US15331366

申请日：2016-10-21

Applicant: ASM IP HOLDING B.V.

Inventor： Antti Juhani Niskanen ,  Jaakko Anttila

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/306

Abstract: Methods for removing a passivation film from a copper surface can include exposing the passivation film to a vapor phase organic reactant, for example at a temperature of 100° C. to 400° C. In some embodiments, the passivation film may have been formed by exposure of the copper surface to benzotriazole, such as can occur during a chemical mechanical planarization process. The methods can be performed as part of a process for integrated circuit fabrication. A second material can be selectively deposited on the cleaned copper surface relative to another surface of the substrate.

公开(公告)号：US20180301460A1

公开(公告)日：2018-10-18

申请号：US15951626

申请日：2018-04-12

Applicant: ASM IP Holding B.V.

Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311

Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.

公开(公告)号：US20180286638A1

公开(公告)日：2018-10-04

申请号：US15890850

申请日：2018-02-07

Applicant: ASM IP Holding B.V.

Inventor： Yoshio SUSA

IPC: H01J37/32

Abstract: A substrate processing apparatus includes a chamber, a susceptor provided in the chamber, a shower plate having a plate part provided with a plurality of through holes and formed of a conductor, a ring-shaped part connected to an outer edge of the plate part, surrounding the plate part and formed of a conductor and a lead wire embedded in the ring-shaped part and surrounding the plate part and the susceptor in plan view, the shower plate being provided so as to face the susceptor in the chamber, and a DC power supply that supplies a direct current to the lead wire.

公开(公告)号：USD829306S1

公开(公告)日：2018-09-25

申请号：US29570199

申请日：2016-07-06

Applicant: ASM IP Holding B.V.

Designer： Yozo Ikedo ,  Takafumi Hisamitsu

公开(公告)号：US10083836B2

公开(公告)日：2018-09-25

申请号：US14808979

申请日：2015-07-24

Applicant: ASM IP Holding B.V.

Inventor： Robert Brennan Milligan

IPC: H01L21/285 ,  H01L21/3205

CPC classification number: H01L21/28562 ,  H01L21/28088 ,  H01L21/32051

Abstract: A method for forming a Boron doped metallic film, such as Titanium Boron Nitride, is disclosed. The method allows for creation of the metallic film with a high work function and low resistivity, while limiting the increase in effective oxide thickness. The method comprises a thin metallic layer deposition step as well as a Boron-based gas pulse step. The Boron-based gas pulse deposits Boron and allows for the removal of excess halogens within the metallic film. The steps may be repeated in order to achieve a desired thickness of the metallic film.

公开(公告)号：US10074541B2

公开(公告)日：2018-09-11

申请号：US15645059

申请日：2017-07-10

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Jaakko Anttila

IPC: H01L21/285 ,  C23C16/34 ,  C23C16/455 ,  H01L23/532 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/28556 ,  C23C16/34 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238

Abstract: In one aspect, methods of forming smooth ternary metal nitride films, such as TixWyNz films, are provided. In some embodiments, the films are formed by an ALD process comprising multiple super-cycles, each super-cycle comprising two deposition sub-cycles. In one sub-cycle a metal nitride, such as TiN is deposited, for example from TiCl4 and NH3, and in the other sub-cycle an elemental metal, such as W, is deposited, for example from WF6 and Si2H6. The ratio of the numbers of each sub-cycle carried out within each super-cycle can be selected to achieve a film of the desired composition and having desired properties.

公开(公告)号：US20180233372A1

公开(公告)日：2018-08-16

申请号：US15434051

申请日：2017-02-15

Applicant: ASM IP HOLDING B.V.

Inventor： Katja Väyrynen ,  Ritala Mikko ,  Markku Leskelä

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/06 ,  H01L21/768

Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.

公开(公告)号：US20180223424A1

公开(公告)日：2018-08-09

申请号：US15945863

申请日：2018-04-05

Applicant: ASM IP Holding B.V.

Inventor： Young-Jae KIM ,  Ki Jong KIM ,  Dong-Rak JUNG ,  Hak Yong KWON ,  Seung Woo CHOI

IPC: C23C16/44 ,  C23C16/458 ,  H01L21/687

CPC classification number: C23C16/4401 ,  C23C16/4586 ,  H01L21/68742

Abstract: A deposition apparatus is provided to eliminate unnecessary empty spaces that may form between a substrate and a substrate supporting pin, which may be formed within a substrate supporting pin hole, by covering the substrate supporting pin, inserted into the substrate supporting pin hole formed in the substrate support, by a substrate supporting pin cover loaded on the substrate support. Accordingly, the temperature under the substrate can be maintained constant, and generation of parasitic plasma or contaminating particles can be avoided.

公开(公告)号：US20180195174A1

公开(公告)日：2018-07-12

申请号：US15402993

申请日：2017-01-10

Applicant: ASM IP Holding B.V.

Inventor： Hyeongeu Kim ,  Tom Kirschenheiter ,  Eric Hill ,  Mark Hawkins ,  Loren Jacobs

IPC: C23C16/52 ,  C23C16/24 ,  C23C16/458

CPC classification number: C23C16/52 ,  C23C16/24 ,  C23C16/4401 ,  C23C16/4411 ,  C23C16/4586

Abstract: A system and method for depositing a film within a reaction chamber are disclosed. An exemplary system includes a temperature measurement device, such as a pyrometer, to measure an exterior wall surface of the reaction chamber. A temperature of the exterior wall surface can be controlled to mitigate cleaning or etching of an interior wall surface of the reaction chamber.