公开(公告)号：US20140084883A1

公开(公告)日：2014-03-27

申请号：US13856611

申请日：2013-04-04

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： HIROHISA TANABE

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract translation: “无窗”H桥降压升压开关转换器包括具有产生“comp”信号的误差放大器的调节电路，将“comp”与“斜坡”信号进行比较的比较电路和接收比较的逻辑电路 电路输出和指示转换器是否以降压模式或升压模式操作的模式控制信号，并分别操作一级或二级开关元件以产生降压或升压模式中的期望输出电压。 “斜坡”信号发生电路在从降压转换到升压模式时将“斜坡”信号向上移动一个电压Vslp（p-p）+ Vhys，并将“斜坡”下移Vslp（p-p） + Vhys从升压转换到降压模式，从而使转换器只能在降压模式或升压模式下工作，无需中间降压 - 升压区域。

公开(公告)号：US20130293405A1

公开(公告)日：2013-11-07

申请号：US13747892

申请日：2013-01-23

Applicant: Italo Carlos Medina Sánchez-Castro

Inventor： Italo Carlos Medina Sánchez-Castro

IPC: H03M1/78

CPC classification number: H03M1/785 ,  H03M1/687 ,  H03M1/745 ,  H03M1/765

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract translation: 数模转换器（DAC）的数字输入被分为最重要的部分和较小的显着部分。 至少一个抽头电压发生器产生多个电压，优选使用电阻串。 解码器解码形成较小有效部分的至少一个子字，以生成对应的至少一个控制信号。 开关单元响应于至少一个控制信号访问由至少一个抽头电压发生器产生的电压。 定标电流发生器从每个访问电压产生相应的加权电流。 输出级将所有加权电流与作为数字输入的最高有效部分的模拟表示的电压组合以产生整个数字输入的模拟近似。

公开(公告)号：US20160105194A1

公开(公告)日：2016-04-14

申请号：US14511613

申请日：2014-10-10

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： MAHESH MADHAVAN KUMBARANTHODIYIL ,  Sandeep Monangi

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/122 ,  H03M1/466

Abstract: In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.

Abstract translation: 在示例实施例中，提供了一种促进被动模拟采样和保持的模数转换器（ADC），并且包括一对二进制加权转换电容器阵列，一对采样电容器和配置每个转换电容器阵列的多个开关 用于采样相位的采样电容器，电荷转移阶段和位试验阶段。 在采样阶段，采样电容器与转换电容器分离并耦合到模拟输入电压。 在电荷转移阶段期间，采样电容器耦合到转换电容器并与模拟输入电压分离。 在位试验阶段，采样电容器与转换电容器分离。

公开(公告)号：US20160099692A1

公开(公告)日：2016-04-07

申请号：US14504540

申请日：2014-10-02

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： VINAYAK MUKUND KULKARNI

IPC: H03F3/16

CPC classification number: H03F3/45183 ,  H03F2203/45248 ,  H03F2203/45626 ,  H03F2203/45644 ,  H03F2203/45646

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract translation: 在示例实施例中，提供了具有高增益和高转换速率的放大器，并且包括一对输入电压施加到的输入晶体管，耦合到输入晶体管的一对二极管连接的负载，至少一对电流源 耦合到所述二极管连接的负载，以及偏置控制，被配置为关断所述至少一对电流源，以使所述放大器能够实现高转换速率，并且接通所述至少一对电流源，以使所述至少一对电流源能够获得高增益 放大器 在具体实施例中，电流源包括晶体管，偏置控制控制到电流源的偏置电压，偏置电压被驱动到电源电压（VDD）以截止电流源。

公开(公告)号：US20160072275A1

公开(公告)日：2016-03-10

申请号：US14477236

申请日：2014-09-04

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： TREVOR CLIFFORD CALDWELL ,  COREY PETERSEN ,  DAVID NELSON ALLDRED ,  HAJIME SHIBATA

IPC: H02H7/12 ,  H03M3/00

CPC classification number: H02H7/12 ,  H03M3/30 ,  H03M3/36 ,  H03M3/464 ,  H03M3/484

Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.

Abstract translation: Δ-Σ调制器不能很好地处理过载，如果输入超出调制器的满量程范围，通常会变得不稳定。 为了提供过载保护，改进的技术将过载检测器嵌入到Δ-Σ调制器中。 当检测到过载条件时，调节ΔΣ调制器的系数以适应过载输入。 改进的技术有利地允许Δ-Σ调制器在没有复位的情况下优雅地处理过载，并且以降低的分辨率提供更大的动态范围。 此外，可以以这样的方式调整Δ-Σ调制器的系数，以确保噪声传递函数不受影响。

公开(公告)号：US20150222288A1

公开(公告)日：2015-08-06

申请号：US14173407

申请日：2014-02-05

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Christopher Peter Hurrell

IPC: H03M1/44 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03G3/3052 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0678 ,  H03M1/12 ,  H03M1/1295 ,  H03M1/468 ,  H03M1/804

Abstract: Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase.

Abstract translation: 本公开的示例性实施例可以提供一种装置，系统和校正由于执行模数转换而从采样电容器损失的电荷的方法。 在一个实施例中，提供了一种操作模数转换器的方法，该方法至少包括用于对输入信号进行采样的第一采样电容器，其中该方法还可以包括校正步骤，该校正步骤修改至少第一采样电容器 ，所述校正步骤在开始获取阶段之前执行。

公开(公告)号：US20150194879A1

公开(公告)日：2015-07-09

申请号：US14147228

申请日：2014-01-03

Applicant: Analog Devices Technology

Inventor： Roger Peppiette ,  Yanfeng Lu ,  Bin Shao ,  Linus Sheng

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract translation: 本应用程序还讨论了升压电路的设备和方法。 在一个示例中，升压电路可以包括第一和第二反相器，共享第一电源节点，并共享第二电源节点，第一电荷转移电容器，被配置为将第一时钟信号耦合到第一反相器输出;第二充电 转移电容器，被配置为将第二时钟信号耦合到第二反相器输出，第二时钟信号与第一时钟信号异相;第一栅极驱动电容器，被配置为将第一时钟信号耦合到第二反相器输入 以及第二栅极驱动电容器，被配置为将所述第二时钟信号耦合到所述第一反相器输入。

公开(公告)号：US20150180425A1

公开(公告)日：2015-06-25

申请号：US14139672

申请日：2013-12-23

Applicant: Analog Devices Technology

Inventor： Dzianis Lukashevich

IPC: H03F1/30

CPC classification number: H03F1/30 ,  H01L27/1203 ,  H03F2200/447 ,  H03F2200/468 ,  H03F2200/528

Abstract: This disclosure relates to temperature stabilization of at least a portion of an amplifier, such as a logarithmic amplifier, and/or a band gap reference circuit. In one aspect, one or more stages of an amplifier, a heater, and a temperature sensor are included in a semiconductor material and surrounded by thermally insulating sidewalls.

Abstract translation: 本公开涉及放大器，例如对数放大器和/或带隙基准电路的至少一部分的温度稳定。 在一个方面，放大器，加热器和温度传感器的一个或多个级包括在半导体材料中并被隔热侧壁包围。

公开(公告)号：US20150115923A1

公开(公告)日：2015-04-30

申请号：US14064490

申请日：2013-10-28

Applicant: Analog Devices Technology

Inventor： Bin Shao

IPC: H02M3/158 ,  H02M3/157

CPC classification number: H02M3/158 ,  H02M3/157 ,  H02M2001/0009

Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.

Abstract translation: 开关调节器或其他装置或技术可以包括负载电流监视以提供估计负载电流的数字表示。 负载电流监视可以由包括计数器电路，比较器电路和耦合到计数器电路的数字控制源的电路执行，并且被配置为响应于由计数器电路提供的计数来调整感测装置的偏置条件 以便建立由感测装置传导的电流与由电力开关装置传导的对应电流之间的比例关系。 计数器电路被配置为响应于由比较器输出提供的信息而增加和减少计数，并且计数通常表示估计的负载电流，例如平均负载电流。

公开(公告)号：US20150109157A1

公开(公告)日：2015-04-23

申请号：US14055980

申请日：2013-10-17

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Trevor Clifford Caldwell ,  Richard E. Schreier

IPC: H03M3/00

CPC classification number: H03M3/458 ,  G01R19/25 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract translation: Δ-Σ调制器被配置为感测并将电磁场转换成数字信号。 示例性的Δ-Σ调制器包括诸如LC谐振器的传感器组件，其被配置为感测电磁场并产生输入模拟信号，其中Δ-Σ调制器被配置为将输入的模拟信号转换为数字信号 。 Δ-Σ调制器可以包括耦合到传感器组件的模数转换器，其接收并将输入的模拟信号转换成数字信号。 Δ-Σ调制器还可以包括耦合到谐振器和ADC的数模转换器（DAC），DAC被配置为从ADC接收数字信号并产生反馈模拟信号。