公开(公告)号：US09164517B2

公开(公告)日：2015-10-20

申请号：US13214426

申请日：2011-08-22

Applicant: Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

Inventor： Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

IPC: G05D16/00 ,  G05D7/06 ,  B01J19/00

CPC classification number: G05D7/0635 ,  B01J19/0046 ,  B01J2219/00286 ,  B01J2219/00306 ,  B01J2219/00337 ,  B01J2219/00389 ,  B01J2219/00418 ,  B01J2219/00479 ,  B01J2219/00585 ,  B01J2219/00698 ,  B01J2219/0072 ,  B01J2219/00756 ,  Y10T137/0379 ,  Y10T137/3115 ,  Y10T137/3127 ,  Y10T137/4807

Abstract: A pressure gauge may be coupled to a supply line which carries liquid from a bottle to either one or more mixing vessels and/or one or more reactors in a combinatorial processing tool. A control device may monitor the pressure measured by the pressure gauge, and the control device may be configured to change the pressure supplied to the bottle based on a comparison of the measured pressure to a predetermined pressure value. The control device may adjust the pressure provided to the bottle using a pressure regulator coupled to the pressure source. By changing the pressure provided to the bottle, the control device may maintain a relatively constant flow rate of fluids from the liquid source into one or more mixing vessels and/or the one or more reactors.

Abstract translation: 压力计可以耦合到供应管线，其将液体从瓶运送到组合加工工具中的一个或多个混合容器和/或一个或多个反应器。 控制装置可以监测由压力计测量的压力，并且控制装置可以被配置成基于测量的压力与预定压力值的比较来改变供给到瓶子的压力。 控制装置可以使用耦合到压力源的压力调节器来调节提供给瓶子的压力。 通过改变提供给瓶子的压力，控制装置可以保持流体从液体源到一个或多个混合容器和/或一个或多个反应器的相对恒定的流速。

公开(公告)号：US20150291812A1

公开(公告)日：2015-10-15

申请号：US14250210

申请日：2014-04-10

Applicant: INTERMOLECULAR INC.

Inventor： Abraham Anapolsky ,  Scott Jewhurst ,  Daniel Schweigert

IPC: C09D5/32 ,  C23C16/515 ,  C23C16/513 ,  C23C28/04 ,  C23C16/42

CPC classification number: C09D5/32 ,  C03C17/36 ,  C03C17/3626 ,  C03C17/3644 ,  C03C17/366 ,  C09D5/004 ,  C23C14/04 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345

Abstract: Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. The optical properties of the coating (e.g. the transmissivity and the IR emissivity) are generally coupled. In some embodiments, silicate materials are doped with rare earth elements. These doped silicate materials are able to absorb ultra-violet (UV) photons and emit photons in the visible range. This allows the transmissivity to be at least partially decoupled from the IR emissivity of the coated panel, resulting in a larger range of performance.

Abstract translation: 公开了由方法制造的方法和涂层板，以在热处理之前和之后形成多个涂层（例如，一个或多个红外反射层），具有最小的颜色变化。 涂层的光学性质（例如透射率和IR辐射率）通常是耦合的。 在一些实施例中，硅酸盐材料掺杂有稀土元素。 这些掺杂的硅酸盐材料能够吸收紫外（UV）光子并发射可见光范围内的光子。 这允许透射率至少部分地与涂覆面板的IR发射率去耦合，导致更大的性能范围。

公开(公告)号：US09147841B2

公开(公告)日：2015-09-29

申请号：US14614143

申请日：2015-02-04

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Chi-I Lang ,  Prashant B. Phatak

IPC: H01L21/336 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1641

Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.

Abstract translation: 描述电阻式切换存储元件。 所述存储元件包括第一电极，所述第一电极上的多孔层，包括嵌入所述多孔层的多个孔中的点缺陷，以及位于所述多孔层上的第二电极，其中所述非易失性存储元件构造成在 高电阻状态和低电阻状态。

公开(公告)号：US09129894B2

公开(公告)日：2015-09-08

申请号：US13621371

申请日：2012-09-17

Applicant: Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

Inventor： Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

IPC: G11C11/21 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

公开(公告)号：US09121100B2

公开(公告)日：2015-09-01

申请号：US13715477

申请日：2012-12-14

Applicant: Intermolecular Inc.

Inventor： Mohd Fadzli Anwar Hassan ,  Guowen Ding ,  Minh Huu Le ,  Minh Anh Anh Nguyen ,  Zhi-Wen Wen Sun ,  Guizhen Zhang

IPC: C23C28/00 ,  C23C30/00 ,  H01L51/52 ,  H01L51/00

CPC classification number: H05K1/092 ,  C23C28/42 ,  C23C30/00 ,  H01L51/0097 ,  H01L51/5234 ,  H05K1/0274 ,  Y10T428/265

Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack to have an improved ductility property.

Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，允许导电叠层具有改善的延展性。

公开(公告)号：US20150228710A1

公开(公告)日：2015-08-13

申请号：US14177118

申请日：2014-02-10

Applicant: Elpida Memory, Inc ,  Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Naonori Fujiwara ,  Imran Hashim ,  Kenichi Koyanagi

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G4/1236 ,  H01G4/33 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/56 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (

Abstract translation: 用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料和轻掺杂或非掺杂材料形成多层电介质叠层。 退火步骤后，高掺杂材料将保持无定形（<30％结晶）。 在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。 在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（≥30％结晶）。 高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

公开(公告)号：US09105704B2

公开(公告)日：2015-08-11

申请号：US13722931

申请日：2012-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L21/3065 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。

公开(公告)号：US09105646B2

公开(公告)日：2015-08-11

申请号：US13731548

申请日：2012-12-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

公开(公告)号：US09105563B2

公开(公告)日：2015-08-11

申请号：US13713421

申请日：2012-12-13

Applicant: Intermolecular, Inc.

Inventor： Charlene Chen ,  Tony P. Chiang ,  Chi-I Lang ,  Yun Wang

IPC: G01N21/59 ,  H01L21/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L22/20 ,  G01N21/59 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L22/12 ,  H01L29/1606

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract translation: 一种方法和系统包括第一衬底和第二衬底，每个衬底在光的预定波长处包括预定的基线透射率值，第一衬底上的处理区域通过组合地改变材料，工艺条件，单元工艺中的至少一个和 与所述石墨烯生产相关联的工艺序列，对所述第一衬底上的所述经处理区域执行第一表征测试以产生第一结果，通过改变材料，工艺条件，单位过程中的至少一种以组合方式处理第二衬底上的区域， 以及基于第一表征测试的第一结果与石墨烯生产相关联的处理顺序，对第二衬底上的经处理区域执行第二表征测试以产生第二结果，以及确定第一衬底和第二衬底中的至少一个 基板满足预定的质量阈值 基于第二个结果。

公开(公告)号：US09105527B2

公开(公告)日：2015-08-11

申请号：US14135086

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le

IPC: H01L21/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/465 ,  H01L21/66

CPC classification number: H01L27/1259 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/465 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅极介电沉积，栅极电介质图案化，基于金属的半导体沉积，基于金属的图案化，蚀刻停止沉积，蚀刻停止图案化，源极/漏极沉积或源极/漏极图案化中的至少一个。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。