公开(公告)号：US09813711B2

公开(公告)日：2017-11-07

申请号：US14302940

申请日：2014-06-12

Applicant: Broadcom Corporation

Inventor： Alexander Garland MacInnis ,  Frederick George Walls

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/124 ,  H04N19/63 ,  H04N19/61 ,  H04N19/62 ,  H04N19/18

CPC classification number: H04N19/124 ,  H04N19/18 ,  H04N19/61 ,  H04N19/62 ,  H04N19/63

Abstract: A system implements a hybrid coding mode. The hybrid coding mode may implement a transform to decompose an input stream into frequency components. The frequency components may include frequency bands such as those resulting from a wavelet transform. The frequency components may have associated coefficients which may be determined via the transform. The hybrid coding mode may also implement a predictor-based coding mode. A predictor-based coding mode uses a set of values as predictors for another set of values. The hybrid mode may be implemented by using predictor-based coding to code a portion of the coefficients. For example, a coefficient may be used as a predictor for another coefficient of same frequency component. In some implementations, dynamic selection between a hybrid coding mode and a point coding mode may be used.

公开(公告)号：US20170302477A1

公开(公告)日：2017-10-19

申请号：US15155137

申请日：2016-05-16

Applicant: BROADCOM CORPORATION

Inventor： Mohan Kalkunte ,  Surendra Anubolu ,  Rochan Sankar

IPC: H04L12/64 ,  H04L29/06 ,  H04L12/741 ,  H04L12/26 ,  H04L12/24

CPC classification number: H04L12/6418 ,  H04L43/026 ,  H04L43/04 ,  H04L45/745 ,  H04L63/1425 ,  H04L63/145 ,  H04L69/165 ,  H04L69/22

Abstract: A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

公开(公告)号：US09753474B2

公开(公告)日：2017-09-05

申请号：US14173742

申请日：2014-02-05

Applicant: BROADCOM CORPORATION

Inventor： Jinghua Zhang ,  Ricky Setiawan ,  Jeffrey Norwood Harrison

IPC: G05F1/56 ,  G05F1/575

CPC classification number: G05F1/575 ,  G05F1/56

Abstract: A low-power low-dropout (LDO) voltage regulator device includes an error amplifier, a level-shifter circuit, and an NMOS pass transistor. The error amplifier compares a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and generates an error signal. The level-shifter circuit is coupled to the error amplifier. The NMOS pass transistor provides the regulated output voltage with low dropout operation. The level-shifter circuit can shift a voltage level of the error signal to facilitate the low dropout operation of the NMOS pass transistor.

公开(公告)号：US09749678B2

公开(公告)日：2017-08-29

申请号：US14624544

申请日：2015-02-17

Applicant: BROADCOM CORPORATION

Inventor： Marcus Christopher Kellerman ,  Jeffrey P. Fisher ,  Alex Pelts

IPC: H04N21/434 ,  H04N21/438 ,  H04N21/4405 ,  H04N21/439 ,  H04N21/4402 ,  H04N21/845 ,  H04N5/50 ,  H04N21/43 ,  H04N21/44

CPC classification number: H04N21/4343 ,  H04N5/50 ,  H04N21/4302 ,  H04N21/4347 ,  H04N21/4384 ,  H04N21/4392 ,  H04N21/4398 ,  H04N21/44004 ,  H04N21/440281 ,  H04N21/4405 ,  H04N21/8455

Abstract: A video channel change system may include one or more processors and a memory. The one or more processors may receive first packets including first video frames associated with a first video channel and second packets including second video frames associated with a second video channel. The one or more processors may decode the first packets and display the first video frames while buffering, in a buffer, the second packets. The one or more processors may determine that a packet of the second packets includes a random access point without decoding the packet, discard the second packets from the buffer that were received prior to the packet, buffer additional second packets received subsequent to the packet, and decode the second packets stored in the buffer and display the second video frames included therein, in response to a request to change from the first video channel to the second video channel.

公开(公告)号：US20170244433A1

公开(公告)日：2017-08-24

申请号：US15068225

申请日：2016-03-11

Applicant: Broadcom Corporation

Inventor： Choong Yul CHA ,  Hongrui WANG ,  Ravi GUPTA ,  Ali AFSAHI

IPC: H04B1/04

CPC classification number: H04B1/04

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

公开(公告)号：US20170229860A1

公开(公告)日：2017-08-10

申请号：US15067445

申请日：2016-03-11

Applicant: BROADCOM CORPORATION

Inventor： Kambiz Vakilian ,  Jingguang Wang

IPC: H02J1/00

CPC classification number: H02J1/00 ,  H01L27/00 ,  H01L28/00 ,  H02J9/005 ,  H02J50/80 ,  H02J2009/007 ,  H05B37/0254

Abstract: A system and method includes a power control circuit for controlling first power from a power supply provided to a first circuit includes a first stage and a second stage. The first stage includes a low power energy detector and a first power switch. The low power energy detector is configured to provide second power via the first switch in response to energy. The second stage includes a signal detector configured to detect a characteristic of a signal associated with the energy in response to the second power. The signal detector is configured have the first power provided to the first circuit in response to the characteristic being detected.

公开(公告)号：US20170228335A1

公开(公告)日：2017-08-10

申请号：US15063387

申请日：2016-03-07

Applicant: BROADCOM CORPORATION

Inventor： Surendra ANUBOLU ,  Mohan Venkatachar KALKUNTE

IPC: G06F13/40 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F13/4022 ,  G06F9/4881 ,  G06F13/4282

Abstract: A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.

公开(公告)号：US09727514B2

公开(公告)日：2017-08-08

申请号：US14590780

申请日：2015-01-06

Applicant: BROADCOM CORPORATION

Inventor： Desheng Ma ,  Derek Hing Sang Tam ,  Chia-Jen Hsu ,  Preeti Mulage

IPC: G06F13/38 ,  G06F13/40 ,  G06F1/32 ,  G06F13/42

CPC classification number: G06F13/4059 ,  G06F1/3287 ,  G06F13/385 ,  G06F13/4295 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

公开(公告)号：US09712231B2

公开(公告)日：2017-07-18

申请号：US14252646

申请日：2014-04-14

Applicant: BROADCOM CORPORATION

Inventor： Yong Liu ,  Ron Porat ,  Nihar Jindal ,  Vinko Erceg ,  Matthew James Fischer ,  Chiu Ngok Eric Wong

IPC: H04B7/26 ,  H04W74/00

CPC classification number: H04B7/2612 ,  H04W74/006

Abstract: A wireless communication device is implemented to include a communication interface and a processor. The processor is configured to process communications associated with the other wireless communication devices within the wireless communication system to determine one or more traffic characteristics of those communications as well as one or more class characteristics of the other wireless communication devices. The processor is configured to classify the communications into one or more access categories based on the one or more traffic characteristics and is configured to classify the other devices into one or more device class categories based on the one or more class characteristics. The processor is then configured to generate one or more channel access control signals based on these classifications. The communication interface of the device is configured to transmit the one or more channel access control signals to one or more of the other devices.

公开(公告)号：US20170199226A1

公开(公告)日：2017-07-13

申请号：US15051134

申请日：2016-02-23

Applicant: Broadcom Corporation

Inventor： Timothy SCRANTON ,  Michael BOERS ,  Seunghwan YOON ,  Jesus CASTANEDA

IPC: G01R1/073 ,  G01R31/28 ,  H01P5/12

CPC classification number: G01R1/0735 ,  G01R1/0416 ,  G01R31/2831 ,  H01P5/028 ,  H01P5/12

Abstract: The present disclosure describes a semiconductor wafer testing environment for routing signals used for testing integrated circuits formed onto a semiconductor wafer. The semiconductor wafer testing environment includes a semiconductor wafer tester to control overall operation and/or configuration of the semiconductor wafer testing environment and a semiconductor wafer prober to test the integrated circuits formed onto the semiconductor wafer. The semiconductor wafer prober includes a probe card having a transmission line coupler formed onto a flexible substrate. The transmission line coupler includes multiple transmission line coupling blocks that extend radially from a central point of the flexible substrate in a circular manner.