公开(公告)号：US20130206586A1

公开(公告)日：2013-08-15

申请号：US13493425

申请日：2012-06-11

Applicant: Wen-Chang LIN

Inventor： Wen-Chang LIN

IPC: C25B1/06

CPC classification number: A61M16/10 ,  A61M16/101 ,  A61M2202/0208 ,  A61M2205/75 ,  A61M2205/8231 ,  C25B1/04 ,  C25B9/06 ,  C25B15/02 ,  Y02E60/366

Abstract: An apparatus that can supply oxyhydrogen gas includes an electrolysis device, a filter device, and a control device. The electrolysis device includes a voltage controller that applies voltages to positive and negative electrode plates to convert water electrolytically in an electrolysis chamber to form oxyhydrogen gas, which is outputted via a first output conduit. An output end of the first output conduit is extended below water level in a container of the filter device. A second output conduit permits the oxyhydrogen gas that flows through the first output conduit and through the water in the container to flow therethrough. The control device includes a ratio adjusting interface for controlling a difference in the voltages provided by the voltage controller so as to adjust a ratio of hydrogen to oxygen in the oxyhydrogen gas formed in the electrolysis chamber.

Abstract translation: 可以提供氢氧气体的装置包括电解装置，过滤装置和控制装置。 电解装置包括电压控制器，其向正极板和负极板施加电压，以在电解室中电解转化水以形成通过第一输出导管输出的氢氧气体。 第一输出管道的输出端在过滤器装置的容器中延伸到水位以下。 第二输出管道允许流过第一输出导管并穿过容器中的水的氢氧气流过其中。 控制装置包括比例调整接口，用于控制由电压控制器提供的电压差，以便调节在电解室中形成的氢氧气体中的氢与氧的比例。

公开(公告)号：US20130194206A1

公开(公告)日：2013-08-01

申请号：US13536645

申请日：2012-06-28

Applicant: Chih-Chiang Chang ,  Chih-Hao Chen ,  Han-Chang Lin ,  Cho-Yi Lin

Inventor： Chih-Chiang Chang ,  Chih-Hao Chen ,  Han-Chang Lin ,  Cho-Yi Lin

IPC: G06F3/041

CPC classification number: G06F3/04883

Abstract: A switching method for an electronic device having sensing regions is mentioned. The switching method is configured to detect signals received by the electronic device, so as to switch the states of the electronic device. The switching method comprises receiving a first signal at a first moment and receiving a second signal at a second moment, wherein the first signal is generated by touching a first sensing region and the second signal is generated by touching a second sensing region; measuring a triggering duration and determining whether the triggering duration is consistent with a predetermined duration, when the first signal and the second signal are inputted simultaneously; switching the electronic device from a first state to a second state, if the triggering duration is consistent with the predetermined duration; and maintaining the electronic device in the first state, if the triggering duration is not consistent with the predetermined duration.

Abstract translation: 提及具有感测区域的电子设备的切换方法。 切换方法被配置为检测由电子设备接收的信号，以便切换电子设备的状态。 切换方法包括在第一时刻接收第一信号并在第二时刻接收第二信号，其中通过触摸第一感测区域产生第一信号，并且通过触摸第二感测区域产生第二信号; 当同时输入第一信号和第二信号时，测量触发持续时间并确定触发持续时间是否与预定持续时间一致; 如果触发持续时间与预定持续时间一致，则将电子设备从第一状态切换到第二状态; 并且如果触发持续时间与预定持续时间不一致，则将电子设备维持在第一状态。

公开(公告)号：US20130190482A1

公开(公告)日：2013-07-25

申请号：US13560593

申请日：2012-07-27

Applicant: Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

Inventor： Hua-Wen Fu ,  Kuo-Shun Shih ,  Chih-Chang Lin ,  Yu-Chi Yang

IPC: C07K1/22

CPC classification number: C07K14/205

Abstract: Helicobacter pylori is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. Helicobacter pylori neutrophil-activating protein (HP-NAP), a virulence factor of Helicobacter pylori, plays an important role in pathogenesis of Helicobacter pylori infection. Since HP-NAP has been proposed as a candidate vaccine against Helicobacter pylori infection, an efficient way to obtain pure HP-NAP needs to be developed. In the present invention, recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli was purified through a single step of DEAE Sephadex ion-exchange chromatography with high purity. Also, purified recombinant HP-NAP was able to stimulate neutrophils to produce reactive oxygen species. Thus, recombinant HP-NAP obtained from our Bacillus subtilis expression system and Escherichia coli expression system is functionally active. Furthermore, this one-step negative purification method should provide an efficient way to purify recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli for basic studies, vaccine development, or drug design.

Abstract translation: 幽门螺杆菌与慢性胃炎，消化性溃疡病和胃腺癌密切相关。 幽门螺杆菌嗜中性粒细胞激活蛋白（HP-NAP）是幽门螺杆菌的毒力因子，在幽门螺杆菌感染的发病机制中起重要作用。 由于HP-NAP已被提出作为针对幽门螺杆菌感染的候选疫苗，因此需要开发获得纯HP-NAP的有效途径。 在本发明中，通过单纯DEAE Sephadex离子交换层析纯化纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP。 此外，纯化的重组HP-NAP能够刺激嗜中性粒细胞产生活性氧。 因此，从我们的枯草芽孢杆菌表达系统和大肠杆菌表达系统获得的重组HP-NAP在功能上是活性的。 此外，该一步负纯化方法应提供一种有效的方法来纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP用于基础研究，疫苗开发或药物设计。

公开(公告)号：US08493124B2

公开(公告)日：2013-07-23

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Ming-Chieh Huang ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。

公开(公告)号：US20130140708A1

公开(公告)日：2013-06-06

申请号：US13309559

申请日：2011-12-02

Applicant: Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

Inventor： Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

IPC: H01L23/498 ,  H01L21/76

CPC classification number: H01L21/76898 ,  H01L21/76232 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供了具有面向第一面的第一面和第二面的半导体衬底。 至少一个开口设置在第一侧限定的保护区域的半导体衬底中。 在第一侧和第二侧上形成第一材料层，第一材料层部分地填充开口。 随后，去除第一侧的第一材料层和保护区域外部的一部分。 在第一侧和第二侧上形成第二材料层，并且第二材料层填充开口。 然后，去除保护区域的第一侧和外侧的第二材料层的一部分。 最后，剩余的第一材料层和第一侧的剩余的第二材料层被平坦化。

公开(公告)号：US08441134B2

公开(公告)日：2013-05-14

申请号：US13228549

申请日：2011-09-09

Applicant: Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/52 ,  H01L23/48 ,  H01L27/146 ,  H01L27/148

CPC classification number: H01L23/12 ,  H01L21/563 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.

Abstract translation: 芯片堆叠结构包括第一芯片和第二芯片。 第一芯片包括具有形成在其上的第一组焊盘的表面，并且第二芯片包括具有形成在其上的第二组焊盘的表面。 第二组垫被粘合到第一组垫上以限定沿相同方向延伸的多个毛细通道。 芯片堆叠结构还包括在第一芯片和第二芯片之间的底部填充填充间隙。 芯片堆叠结构能够在焊接过程中避免芯片变形和开裂。

公开(公告)号：US08436671B2

公开(公告)日：2013-05-07

申请号：US12859456

申请日：2010-08-19

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

IPC: H03L5/00

CPC classification number: H03K3/02 ,  H03K19/018521 ,  H03K19/018528

Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

Abstract translation: 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

公开(公告)号：US08429326B2

公开(公告)日：2013-04-23

申请号：US11162465

申请日：2005-09-12

Applicant: Huey-Tyug Chua ,  Yann-Chang Lin ,  Ching-Lin Hsu

Inventor： Huey-Tyug Chua ,  Yann-Chang Lin ,  Ching-Lin Hsu

IPC: G06F12/00

CPC classification number: G11C16/20

Abstract: A method and system for identifying a NAND-Flash without reading a device ID. The method includes: executing an identification flow for setting a first page of a block as a target block, utilizing a combinations table to query a target block, evaluating a result by comparing a identifying information in the target block with the combinations table, trying all combinations in the combinations table until correctly identifying the NAND-Flash by having a positive match result or returning an error if none of the combinations match.

Abstract translation: 一种用于在不读取设备ID的情况下识别NAND闪存的方法和系统。 该方法包括：执行用于将块的第一页面设置为目标块的标识流，利用组合表来查询目标块，通过将目标块中的识别信息与组合表进行比较来评估结果，尝试全部 组合表中的组合，直到通过具有正匹配结果正确识别NAND闪存或者如果没有组合匹配则返回错误。

公开(公告)号：US08421242B2

公开(公告)日：2013-04-16

申请号：US12651087

申请日：2009-12-31

Applicant: Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Chang-Lin Yeh ,  Ming-Hsiang Cheng

Inventor： Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Chang-Lin Yeh ,  Ming-Hsiang Cheng

IPC: H01L23/48

CPC classification number: H01L23/16 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/562 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Abstract translation: 提供半导体封装。 半导体封装包括有机衬底，刚度层和芯片子组件。 刚性层形成在有机基底上。 芯片组件设置在刚度层上。 芯片子组件至少包括第一芯片，第二芯片和第三芯片。 第二芯片以堆叠取向布置在第一芯片和第三芯片之间。 第一芯片，第二芯片和第三芯片具有接近通信的功能。

公开(公告)号：US08415732B2

公开(公告)日：2013-04-09

申请号：US11927700

申请日：2007-10-30

Applicant: Yi-Nan Su ,  Yung-Chang Lin ,  Jun-Chi Huang

Inventor： Yi-Nan Su ,  Yung-Chang Lin ,  Jun-Chi Huang

IPC: H01L27/108

CPC classification number: H01L27/1087

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract translation: 公开了一种制造沟槽电容器的方法。 提供具有第一焊盘层的衬底。 STI结构嵌入到第一焊盘层和衬底中。 在第一焊盘层和STI结构上沉积第二焊盘层。 两个相邻的沟槽被蚀刻到第一，第二焊盘层和半导体衬底中。 蚀刻第二焊盘层和两个沟槽之间的STI结构的一部分以形成脊。 衬套形成在沟槽的内表面上。 在衬套上形成第一多晶硅层。 在第一多晶硅层上形成电容器电介质层。 两个相邻的沟槽被填充有第二多晶硅层。 然后蚀刻第二多晶硅层直到暴露电容器介电层。 制造工艺易于集成到SoC芯片。