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    Floating gate and fabrication method therefor
    31.
    发明申请
    Floating gate and fabrication method therefor 审中-公开
    浮门及其制造方法

    公开(公告)号：US20050101090A1

    公开(公告)日：2005-05-12

    申请号：US11014483

    申请日：2004-12-15

    Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

    CPC classification number: H01L29/42324 ,  H01L29/40114

    Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

    Abstract translation: 具有多个尖端的浮动栅极及其制造方法。 提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。 在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。 间隔件形成在开口的侧壁上。 导电间隔件形成在间隔件的侧壁上。 第一导电层被蚀刻到第二预定厚度。 由第一导电层和导电间隔物提供多尖端浮栅。 在开口中形成保护层。 蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。

    Method for manufacturing a self-aligned split-gate flash memory cell
    32.
    发明授权
    Method for manufacturing a self-aligned split-gate flash memory cell 有权
    用于制造自对准分裂闸闪存单元的方法

    公开(公告)号：US06800526B2

    公开(公告)日：2004-10-05

    申请号：US10302865

    申请日：2002-11-25

    Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

    Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

    IPC: H01L21336

    CPC classification number: H01L29/42332 ,  H01L21/28273

    Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

    Abstract translation: 一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口 去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

    Method of fabricating a flash memory cell
    33.
    发明授权
    Method of fabricating a flash memory cell 有权
    制造闪存单元的方法

    公开(公告)号：US06673676B2

    公开(公告)日：2004-01-06

    申请号：US10229529

    申请日：2002-08-27

    Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

    Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

    IPC: H01L21336

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

    Abstract translation: 一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 在所述第一栅极绝缘层上形成第一导电层; 形成浮栅绝缘层; 通过将杂质离子注入衬底来形成源区; 形成第二绝缘层; 形成浮栅区域; 形成第三绝缘层; 在所述第三绝缘层上形成第二导电层; 在所述第二导电层上形成第四绝缘层; 形成浮栅区域; 在所述第三绝缘层上形成第二导电层; 形成第一侧壁间隔物; 形成控制栅极和隧道氧化物; 形成第二侧壁间隔物; 以及在所述衬底上形成漏区。

    MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF
    36.
    发明申请
    MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF 审中-公开
    具有稳定运动的记忆体电容器及其制造方法

    公开(公告)号：US20130168812A1

    公开(公告)日：2013-07-04

    申请号：US13426848

    申请日：2012-03-22

    Applicant: TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

    Inventor： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

    IPC: H01L29/92 ,  H01L21/02

    CPC classification number: H01L28/91 ,  H01L27/10852

    Abstract: A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.

    Abstract translation: 一种具有坚固的护城河的存储电容器的制造方法，包括以下步骤：提供衬底; 在具有护城河的基板上形成图案化的牺牲层以分离单元区域和周边区域; 在所述牺牲层上形成支撑层并填充所述护城河以形成环形构件，其中所述支撑层和所述牺牲层排列成对准以形成堆叠结构; 在所述基板上形成多排电容器沟槽，其中所述电容器沟槽在所述堆叠结构中间隔地形成; 以及在所述支撑层上形成导电层，并覆盖所述基板和限定所述电容器沟槽的所述堆叠结构的内表面。

    HIGH-K METAL GATE RANDOM ACCESS MEMORY
    37.
    发明申请
    HIGH-K METAL GATE RANDOM ACCESS MEMORY 有权
    高K金属门随机存取存储器

    公开(公告)号：US20130168751A1

    公开(公告)日：2013-07-04

    申请号：US13426825

    申请日：2012-03-22

    Applicant: TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

    Inventor： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

    IPC: H01L27/108

    CPC classification number: H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

    Abstract: The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.

    Abstract translation: 本公开涉及高k金属栅极随机存取存储器。 存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。 衬底具有多个沟槽，并且位线单元布置在衬底上。 源极区域设置在位线单元上，栅极结构设置在源极区域上。 每个栅极结构具有形成在其中的金属栅极和沟道区域。 栅极结构顶部带有漏极区域。 字线单元布置在源区和漏区之间。电容单元设置在漏区上。 还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

    Memory layout structure and memory structure
    39.
    发明授权
    Memory layout structure and memory structure 有权
    内存布局结构和内存结构

    公开(公告)号：US08431933B2

    公开(公告)日：2013-04-30

    申请号：US12874232

    申请日：2010-09-02

    Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

    Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

    IPC: H01L29/10

    CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

    Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

    Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

    NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY
    40.
    发明申请
    NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY 有权
    NAND型闪存，用于增加数据读/写可靠性

    公开(公告)号：US20130026556A1

    公开(公告)日：2013-01-31

    申请号：US13224561

    申请日：2011-09-02

    Applicant: TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

    Inventor： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

    IPC: H01L29/788

    CPC classification number: H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

    Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

    Abstract translation: 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元形成在第一电介质层上。 每个数据存储单元包括形成在第一介电层上的两个浮置栅极，分别形成在两个浮置栅极上的两个栅极间电介质层，分别形成在两个栅极间电介质层上的两个控制栅极， 第一电介质层，两个浮置栅极之间，两个栅极间电介质层之间以及两个控制栅极之间，以及形成在第一介电层上并围绕并连接两个浮动栅极的第三介质层， - 门电介质层和两个控制门。

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