公开(公告)号：US20110315543A1

公开(公告)日：2011-12-29

申请号：US12825091

申请日：2010-06-28

申请人： Yongjun Jeff Hu ,  Everett A. McTeer ,  John A. Smythe, III ,  Gurtej S. Sandhu

发明人： Yongjun Jeff Hu ,  Everett A. McTeer ,  John A. Smythe, III ,  Gurtej S. Sandhu

IPC分类号： C23C14/35

CPC分类号： H01J37/3467 ,  C23C14/08 ,  C23C14/082 ,  C23C14/088 ,  C23C14/3407 ,  C23C14/3485 ,  C23C14/35 ,  H01J37/3417 ,  H01J37/3426 ,  H01J2237/3322 ,  H01L21/02192 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

摘要： Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.

摘要翻译： 本文描述了使用高功率脉冲磁控溅射的存储器。 一个或多个方法实施例包括在使用高功率脉冲磁控溅射（HIPIMS）的结构上形成电阻式存储器材料，其中在具有大约400摄氏度或更低的温度的环境中在该结构上形成电阻性存储材料。

公开(公告)号：US07928577B2

公开(公告)日：2011-04-19

申请号：US12174393

申请日：2008-07-16

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L23/52

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US07557420B2

公开(公告)日：2009-07-07

申请号：US11321511

申请日：2005-12-29

申请人： Janos Fucsko ,  John A Smythe, III ,  Li Li ,  Grady S Waldo

发明人： Janos Fucsko ,  John A Smythe, III ,  Li Li ,  Grady S Waldo

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L21/02164 ,  H01L21/02222 ,  H01L21/02236 ,  H01L21/02282 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/76205 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832

摘要： Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

摘要翻译： 公开了利用聚硅氮烷基氧化硅层或填充物的半导体器件，结构和系统以及制造氧化物层的方法。 在一个实施方案中，将聚硅氮烷溶液沉积在基底上，并在低温下经湿氧化处理臭氧，以将聚硅氮烷材料化学改性为氧化硅层。

公开(公告)号：US07271464B2

公开(公告)日：2007-09-18

申请号：US10925715

申请日：2004-08-24

申请人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

发明人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/76227

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。

公开(公告)号：US07112513B2

公开(公告)日：2006-09-26

申请号：US10782997

申请日：2004-02-19

申请人： John A. Smythe, III ,  Jigish D. Trivedi

发明人： John A. Smythe, III ,  Jigish D. Trivedi

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

公开(公告)号：US06436195B1

公开(公告)日：2002-08-20

申请号：US09643777

申请日：2000-08-22

申请人： John A. Smythe ,  John E. Berg

发明人： John A. Smythe ,  John E. Berg

IPC分类号： C23C1600

CPC分类号： H01L21/02274 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3003 ,  H01L21/31625 ,  H01L21/76801

摘要： Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free radicals that are introduced into the dielectric layers. The hydrogen free radicals can affect the stability of the threshold and breakdown voltage of MOSFET transistors. Deuterium introduced into the CVD chamber competes to enter the dielectric layer with the hydrogen. The deuterium prevents some of the hydrogen free radicals from entering the dielectric layer and thus increases MOSFET reliability.

摘要翻译： 沉积的用于半导体器件的电介质层通常在化学气相沉积中形成。 通常形成氢副产物。 特别是在等离子体增强化学气相沉积工艺中，氢副产物可以形成引入电介质层的自由基。 氢自由基可以影响MOSFET晶体管的阈值和击穿电压的稳定性。 引入CVD室的氘与氢气竞争进入电介质层。 氘可防止一些氢自由基进入电介质层，从而提高MOSFET的可靠性。

公开(公告)号：US6156653A

公开(公告)日：2000-12-05

申请号：US962828

申请日：1997-11-03

申请人： John A. Smythe ,  John E. Berg

发明人： John A. Smythe ,  John E. Berg

IPC分类号： C23C16/40 ,  H01L21/30 ,  H01L21/316 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/02274 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3003 ,  H01L21/31625 ,  H01L21/76801

摘要： Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free radicals that are introduced into the dielectric layers. The hydrogen free radicals can affect the stability of the threshold and breakdown voltage of MOSFET transistors. Deuterium introduced into the CVD chamber competes to enter the dielectric layer with the hydrogen. The deuterium prevents some of the hydrogen free radicals from entering the dielectric layer and thus increases MOSFET reliability.