公开(公告)号：US20060097288A1

公开(公告)日：2006-05-11

申请号：US11241604

申请日：2005-09-30

Applicant: In-Gyu Baek ,  Moon-Sook Lee

Inventor： In-Gyu Baek ,  Moon-Sook Lee

IPC: H01L21/82 ,  H01L27/10

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower electrodes are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer is provided between the upper electrodes and the lower electrodes and provided as a data storage material layer. Doped regions are provided between the lower electrodes and the doped lines and form diodes together with the doped lines. The doped regions have an opposite polarity to the doped lines

Abstract translation: 使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件包括设置在衬底中的间隔开的掺杂线。 间隔开的上电极在掺杂线上交叉，使得形成交叉点，其中上电极与掺杂线重叠。 下电极设置在掺杂线和上电极之间的交叉点处。 在上部电极和下部电极之间设置二元金属氧化物层，作为数据存储材料层。 掺杂区域设置在下电极和掺杂线之间，并与掺杂线一起形成二极管。 掺杂区域具有与掺杂线相反的极性

公开(公告)号：US20050064605A1

公开(公告)日：2005-03-24

申请号：US10898564

申请日：2004-07-26

Applicant: Moon-Sook Lee ,  Byoung-Jae Bae

Inventor： Moon-Sook Lee ,  Byoung-Jae Bae

IPC: C23C16/44 ,  C23C16/452 ,  C23C16/455 ,  H01L21/00 ,  H01L21/8242

CPC classification number: C23C16/45565 ,  C23C16/4411 ,  C23C16/452 ,  C23C16/45514

Abstract: Metal organic chemical vapor deposition (MOCVD) may be utilized in methods of forming an (111) oriented PZT ferroelectric layer at a lower temperature, a ferroelectric capacitor and methods of fabricating, and a ferroelectric memory device using the same may be provided. Using the metal organic chemical vapor deposition, ferroelectric layers, capacitors, and memory devices, which may be fabricated and may have (111) preferred oriented crystal growth.

Abstract translation: 金属有机化学气相沉积（MOCVD）可以用于在较低温度下形成（111）取向的PZT铁电体层的方法，铁电电容器和制造方法，并且可以提供使用该方法的铁电存储器件。 使用金属有机化学气相沉积，铁电层，电容器和存储器件，其可以被制造并且可以具有（111）优选的取向晶体生长。

公开(公告)号：US06764862B2

公开(公告)日：2004-07-20

申请号：US10198501

申请日：2002-07-17

Applicant: Kun-Sang Park ,  Moon-Sook Lee

Inventor： Kun-Sang Park ,  Moon-Sook Lee

IPC: H01L2100

CPC classification number: H01L21/7687 ,  H01L21/76802 ,  H01L21/76834 ,  H01L27/11502 ,  H01L27/11507

Abstract: The present invention discloses a method of forming a ferroelectric random access memory (FRAM) of a capacitor over bit-line (COB) structure. In the method, a capacitor contact plug is formed at a cell region and a stud is formed at a core region in a semiconductor substrate. An oxygen barrier pattern is formed to cover the stud. A ferroelectric capacitor comprising a lower electrode, a ferroelectric pattern, and an upper electrode is formed over the capacitor contact plug. An interlayer dielectric layer is formed over substantially the entire surface of the semiconductor substrate and patterned. Next, the interlayer dielectric layer is removed from the stud region and an interconnection contact hole is formed. A contact plug is formed in the interconnection contact hole by sputtering and simultaneously an interconnection layer is formed on the interlayer dielectric layer.

Abstract translation: 本发明公开了一种通过位线（COB）结构形成电容器的铁电随机存取存储器（FRAM）的方法。 在该方法中，在单元区域形成电容器接触插塞，并且在半导体基板的芯区域形成螺柱。 形成氧阻挡图案以覆盖螺柱。 在电容器接触插塞上方形成包括下电极，铁电体图案和上电极的铁电电容器。 在半导体衬底的基本上整个表面上形成层间电介质层并进行图案化。 接下来，从螺柱区域去除层间绝缘层，形成互连接触孔。 通过溅射在互连接触孔中形成接触插塞，同时在层间电介质层上形成互连层。

公开(公告)号：US08105697B2

公开(公告)日：2012-01-31

申请号：US11905510

申请日：2007-10-02

Applicant: Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

Inventor： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

IPC: B21D39/00 ,  B32B9/02

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0035 ,  H01L51/0047 ,  Y10T428/12556 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

Abstract translation: 提供聚合物记忆装置及其形成方法。 聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。 第一电极可以设置在基板上。 第一可固化聚合物层可以覆盖第一电极。 第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。 第二可固化聚合物层可以覆盖第二电极。 第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。 第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。

公开(公告)号：US08022410B2

公开(公告)日：2011-09-20

申请号：US12497852

申请日：2009-07-06

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L27/1292 ,  H01L29/42384

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract translation: 薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。 源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。 源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。 漏极线可以与沟道层接触并且可以与源极线隔开通道长度。 漏极线可以具有与源极线对称的结构。 可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

公开(公告)号：US20100044666A1

公开(公告)日：2010-02-25

申请号：US12612187

申请日：2009-11-04

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: H01L47/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US20090302302A1

公开(公告)日：2009-12-10

申请号：US12533793

申请日：2009-07-31

Applicant: Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

Inventor： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

IPC: H01L45/00 ,  H01L21/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C2213/35 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

Abstract: Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

Abstract translation: 公开了一种金属 - 金属氧化物电阻式存储器件，其包括设置在衬底中的下导电层图案。 绝缘层形成在衬底上，包括用于部分地暴露下导电层图案的上表面的接触孔。 接触孔填充有从下导电层图案生长的碳纳米管。 在碳纳米管和绝缘层上形成由2-组分材料制成的上电极和过渡金属氧化物层。 金属 - 金属氧化物电阻式存储器件适用于高集成度，并通过增加其中的电阻而以相对较小的功耗进行操作。

公开(公告)号：US07521746B2

公开(公告)日：2009-04-21

申请号：US12108255

申请日：2008-04-23

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L27/108

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract translation: 铁电随机存取存储器（FRAM）在衬底上包括半导体衬底和层间绝缘层。 扩散防止层在层间绝缘层上。 扩散防止层和层间绝缘层在其中形成有两个节点接触孔。 节点导电层图案分别与节点接触孔对准，并且被布置成从扩散防止层向上突出。 下电极分别设置在覆盖节点导电层图案的扩散防止层上。 下部电极的厚度从从节点导电层图案的上表面朝向扩散防止层延伸的线逐渐减小。

公开(公告)号：US20090085072A1

公开(公告)日：2009-04-02

申请号：US12232243

申请日：2008-09-12

Applicant: Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue ,  Jung-Hwan Hah

Inventor： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue ,  Jung-Hwan Hah

IPC: H01L21/28 ,  H01L29/772

CPC classification number: G01N27/4145 ,  B82Y10/00 ,  B82Y15/00 ,  G01N27/4146 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

Abstract translation: 实施例涉及使用纳米级材料作为晶体管的沟道的生物传感器及其制造方法。 根据示例性实施例的生物传感器可以包括多个绝缘膜。 第一信号线和第二信号线可以插入在多个绝缘膜之间。 半导体纳米结构可以设置在多个绝缘膜上，半导体纳米结构具有电连接到第一信号线的第一侧和与第二信号线电连接的第二侧。 多个探针可以耦合到半导体纳米结构。 根据示例性实施例的生物传感器可以具有减少的分析时间。

公开(公告)号：US20080131712A1

公开(公告)日：2008-06-05

申请号：US11905510

申请日：2007-10-02

Applicant: Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

Inventor： Byeong-Ok Cho ,  Takahiro Yasue ,  Moon-Sook Lee

IPC: B32B27/06 ,  B05D5/12

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0035 ,  H01L51/0047 ,  Y10T428/12556 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

Abstract translation: 提供聚合物记忆装置及其形成方法。 聚合物记忆装置可以包括第一电极，第一可固化聚合物层，第二电极，第二可固化聚合物层和第三电极。 第一电极可以设置在基板上。 第一可固化聚合物层可以覆盖第一电极。 第二电极可以设置在第一可固化聚合物层上并与第一电极交叉。 第二可固化聚合物层可以覆盖第二电极。 第三电极可以设置在第二可固化聚合物层上并与第二电极交叉。 第一可固化聚合物层和第二可固化聚合物层中的每一个可以含有富勒烯或富勒烯衍生物。