中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

48 records (took 0.022 seconds)

    Local sense amplifier in memory device
    31.
    发明授权
    Local sense amplifier in memory device 失效

    公开(公告)号：US07236414B2

    公开(公告)日：2007-06-26

    申请号：US11179408

    申请日：2005-07-12

    Applicant: Sang-Bo Lee

    Inventor： Sang-Bo Lee

    IPC: G11C7/00

    CPC classification number: G11C7/18 ,  G11C7/062

    Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

    Local sense amplifier in memory device
    32.
    发明申请
    Local sense amplifier in memory device 失效
    存储器中的本地读出放大器

    公开(公告)号：US20060013051A1

    公开(公告)日：2006-01-19

    申请号：US11179408

    申请日：2005-07-12

    Applicant: Sang-Bo Lee

    Inventor： Sang-Bo Lee

    IPC: G11C7/00

    CPC classification number: G11C7/18 ,  G11C7/062

    Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

    Abstract translation: 存储器件包括一个解码器，它同时设置第一逻辑电平的操作控制信号和列选择线信号。 另外，本地读出放大器具有至少一个开关装置，该开关装置由处于第一逻辑电平的操作控制信号导通，以将至少一个本地I / O线耦合到至少一个全局I / O线。 此外，被设置为并联的信号线从解码器发送操作控制信号和列选择线信号。

    Frequency measuring circuits including charge pumps and related memory devices and methods
    33.
    发明申请
    Frequency measuring circuits including charge pumps and related memory devices and methods 失效
    频率测量电路包括电荷泵和相关的存储器件和方法

    公开(公告)号：US20050187724A1

    公开(公告)日：2005-08-25

    申请号：US11031104

    申请日：2005-01-07

    Applicant: Hyun-Jin Kim ,  Sang-Bo Lee

    Inventor： Hyun-Jin Kim ,  Sang-Bo Lee

    IPC: G11C7/00 ,  G06F19/00 ,  G11C7/16 ,  G11C7/22

    CPC classification number: G11C7/22 ,  G11C7/16 ,  G11C7/222

    Abstract: A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.

    Abstract translation: 频率测量电路可以包括边缘检测器，电荷泵和模数（A / D）转换器。 边缘检测器可以被配置为响应于输入时钟信号的边缘产生输出脉冲。 电荷泵可以被配置为响应于来自边缘检测器的输出脉冲而产生输出信号。 模拟数字（A / D）转换器可以被配置为将输出信号转换成表示输入时钟信号的频率的数字值。 还讨论了相关方法和集成电路存储器件。

    Self repairing integrated circuit memory devices and methods
    34.
    发明授权
    Self repairing integrated circuit memory devices and methods 失效
    自修复集成电路存储器件及方法

    公开(公告)号：US5748543A

    公开(公告)日：1998-05-05

    申请号：US705556

    申请日：1996-08-29

    Applicant: Sang-Bo Lee ,  Soo-In Cho

    Inventor： Sang-Bo Lee ,  Soo-In Cho

    IPC: G11C29/00 ,  G11C7/00

    CPC classification number: G11C29/72 ,  G11C29/785

    Abstract: Self repairing integrated circuit memory devices include the plurality of normal memory cells, plurality of spare memory cells and a plurality of spare substituting circuits. A spare substituting circuit is responsive to a defective normal memory cell address which is programmed therein, to substitute at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein. A sequential spare substituting circuit selector is connected to the spare substituting circuits and is responsive to a defect indication signal, to sequentially select a respective one of the spare circuits for programming with sequential ones of the defective normal memory cell addresses. An alarm signal is generated if all of the spare substituting circuits have been used. If a defect is present in at least two normal memory cells in different rows and the same column, a spare column is substituted rather than two spare rows. Also, if all rows substituting circuits have been programmed spare column substituting circuits are used. Defective addresses are programmed using electrically programmable fuses preferably polycrystalline silicon elongated fuses.

    Abstract translation: 自修复集成电路存储器件包括多个正常存储器单元，多个备用存储单元和多个备用替换电路。 备用替代电路响应于其中编程的有缺陷的正常存储器单元地址，以替代至少一个备用存储器单元，该至少一个故障正常存储器单元位于其中编程的故障正常存储器单元地址。 顺序的备用电路选择器连接到备用替代电路，并且响应于缺陷指示信号，顺序地选择备用电路中的相应一个，以用有序的正常存储器单元地址中的顺序选择。 如果已经使用所有备用替换电路，则产生报警信号。 如果在不同行和相同列中的至少两个正常存储单元中存在缺陷，则替换备用列而不是两个备用行。 而且，如果所有行代替电路都被编程，则使用备用列替代电路。 使用电可编程保险丝，优选多晶硅细长型保险丝来编程不良地址。

    SEMICONDUCTOR PACKAGE
    38.
    发明申请
    SEMICONDUCTOR PACKAGE 有权
    半导体封装

    公开(公告)号：US20130037964A1

    公开(公告)日：2013-02-14

    申请号：US13567394

    申请日：2012-08-06

    Applicant: Hoon Lee ,  Sang-Bo Lee

    Inventor： Hoon Lee ,  Sang-Bo Lee

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17517 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

    Abstract: A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.

    Abstract translation: 半导体封装基板可以包括第一半导体芯片，第二半导体芯片，插头和互连端子。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第一和第二半导体芯片可以具有对应的第一区域和对应的第二区域。 导电插头可以仅构建在第一半导体芯片的第一区域中。 第二半导体芯片的电路只能通过对应于第一和第二半导体芯片的第一区域的导电连接器与第一半导体芯片电连接。

    Semiconductor memory device having local sense amplifier with on/off control
    39.
    发明授权
    Semiconductor memory device having local sense amplifier with on/off control 有权
    具有开/关控制的本地读出放大器的半导体存储器件

    公开(公告)号：US07855926B2

    公开(公告)日：2010-12-21

    申请号：US11188184

    申请日：2005-07-20

    Applicant: Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    Inventor： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    IPC: G11C7/00 ,  G11C7/02

    CPC classification number: G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

    Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

    Abstract translation: 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

    Semiconductor memory device capable of reading and writing data at the same time
    40.
    发明授权
    Semiconductor memory device capable of reading and writing data at the same time 有权
    能够同时读取和写入数据的半导体存储器件

    公开(公告)号：US07366822B2

    公开(公告)日：2008-04-29

    申请号：US10840268

    申请日：2004-05-07

    Applicant: Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

    Inventor： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

    IPC: G06F12/00 ,  G11C8/00

    CPC classification number: G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

    Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

    Abstract translation: 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

Patent Agency Ranking