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44 条记录 (耗时 0.013 秒)

    Structure and method to integrate embedded DRAM with FinFET
    34.
    发明授权
    Structure and method to integrate embedded DRAM with FinFET 有权
    嵌入式DRAM与FinFET集成的结构和方法

    公开(公告)号：US08753934B2

    公开(公告)日：2014-06-17

    申请号：US13612069

    申请日：2012-09-12

    申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    IPC分类号： H01L21/48

    CPC分类号： H01L27/10826 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1211

    摘要： Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.

    摘要翻译： 各种实施例将嵌入式动态随机存取存储器与鳍场效应晶体管集成 在一个实施例中，在衬底上形成第一鳍结构和至少第二鳍结构。 在第一和第二翅片结构之间形成深沟槽区域。 在深沟槽区域内形成高k金属栅极。 高k金属栅极包括高k电介质层和金属层。 多晶硅材料沉积在与金属层相邻的深沟槽区域内。 高k金属栅极和多晶硅材料被凹入并蚀刻到衬底绝缘体层的顶表面下方的区域。 在深沟槽区域中形成多晶带。 该多晶带的尺寸设计成在第一和第二鳍结构的顶表面下方。 第一和第二翅片结构电耦合到多晶带。

    High performance non-planar semiconductor devices with metal filled inter-fin gaps
    35.
    发明授权
    High performance non-planar semiconductor devices with metal filled inter-fin gaps 有权

    公开(公告)号：US08653610B2

    公开(公告)日：2014-02-18

    申请号：US12764762

    申请日：2010-04-21

    申请人： Hemanth Jagannathan ,  Sivananda Kanakasabapathy

    发明人： Hemanth Jagannathan ,  Sivananda Kanakasabapathy

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0924 ,  H01L29/7845 ,  H01L29/785

    摘要： A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

    Method of eDRAM DT Strap Formation in FinFET Device Structure
    36.
    发明申请
    Method of eDRAM DT Strap Formation in FinFET Device Structure 有权
    FinFET器件结构中eDRAM DT带形成的方法

    公开(公告)号：US20140027831A1

    公开(公告)日：2014-01-30

    申请号：US13570379

    申请日：2012-08-09

    申请人： Veeraraghavan S. Basker ,  Sivananda Kanakasabapathy ,  Tenko Yamashita ,  Chun-Chen Yeh

    发明人： Veeraraghavan S. Basker ,  Sivananda Kanakasabapathy ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC分类号： H01L27/088

    CPC分类号： H01L27/10867 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1211

    摘要： The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

    摘要翻译： 说明书和附图提出了一种新的方法，设备和计算机/软件相关产品（例如，计算机可读存储器），用于实现Fin FET器件结构中的eDRAM带形成。 提供了在第一半导体层和第二半导体层之间至少包括绝缘体层的半导体绝缘体（SOI）衬底。 （金属）带形成是通过在第二半导体层（Si）的鳍部分上沉积导电层和延伸到第二半导体层的每个DT电容器中的半导体材料（多晶硅）来实现的。 金属带由氮化物间隔物密封，以防止PWL和DT电容器之间的短路。

    Single metal gate CMOS integration by intermixing polarity specific capping layers
    37.
    发明授权
    Single metal gate CMOS integration by intermixing polarity specific capping layers 有权
    单金属门CMOS集成通过混合极性特定的封盖层

    公开(公告)号：US08541275B2

    公开(公告)日：2013-09-24

    申请号：US12616941

    申请日：2009-11-12

    申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Matthew Copel

    发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Matthew Copel

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/3105 ,  H01L21/823842

    摘要： A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer.

    摘要翻译： 用于形成互补金属氧化物半导体器件的方法包括在电介质层上形成第一覆盖层，使用阻挡掩模阻挡覆盖层在要被保持的区域中的部分。 第一覆盖层的暴露部分与电介质层混合以形成第一混合层。 去除块掩模。 蚀刻第一覆盖层和第一混合层，使得除去第一覆盖层以在不去除第一混合层的情况下再次暴露在区域中的电介质层。

    TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN
    38.
    发明申请
    TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开
    带有通道和放大源/漏极的晶体管

    公开(公告)号：US20130175579A1

    公开(公告)日：2013-07-11

    申请号：US13347161

    申请日：2012-01-10

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

    IPC分类号： H01L29/78 ,  H01L21/335

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

    摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

    摘要翻译： 晶体管包括第一半导体层。 第二半导体层位于第一半导体层上。 去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。 栅极间隔物位于第二半导体层上。 栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。 栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。 沟道区位于第一半导体层的第一部分的至少一部分中。 上升的源极/漏极区域位于第二半导体层中。 凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。

    Stacked magnetic devices
    40.
    发明授权
    Stacked magnetic devices 失效
    堆叠式磁性器件

    公开(公告)号：US08120946B2

    公开(公告)日：2012-02-21

    申请号：US12504860

    申请日：2009-07-17

    申请人： Sivananda Kanakasabapathy ,  Yu Lu ,  Michael Christopher Gaidis, III

    发明人： Sivananda Kanakasabapathy ,  Yu Lu ,  Michael Christopher Gaidis, III

    IPC分类号： G11C11/00

    CPC分类号： G11C11/15

    摘要： Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level.

    摘要翻译： 提供了提高磁性器件性能的技术。 在一个方面，提供一种磁性装置，例如磁性随机存取存储装置，其包括多个载流线; 以及两个或更多个相邻的层叠磁性切换装置，其共同地共享多个载流线中的至少一个并且位于它们之间。 磁性装置被配置成使得至少一个相邻的磁性切换装置互相切换另一个相邻的磁性切换装置。 在示例性实施例中，磁性装置包括多个级别，其中每个相邻的层叠磁性切换装置处于不同的水平。