Abstract:
A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture of a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RE) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.
Abstract:
A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.
Abstract:
A method for forming a silicon oxide layer for use in integrated circuit fabrication is provided. The silicon oxide layer is formed by reacting a first gas mixture and a second gas mixture. The first gas mixture comprises tetra-ethyl-ortho-silicate (TEOS), helium (He) and nitrogen (N2). The second gas mixture comprises ozone (O3) and optionally, oxygen (O2).
Abstract:
A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.
Abstract:
The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
Abstract:
The present invention provides a method for cleaning a processing chamber. According to a specific embodiment, the method includes steps of depositing a dielectric film on a wafer on a ceramic heater in the processing chamber in a first time period, with the ceramic heater heated to a first temperature of at least about 500.degree. C. during the deposition step; and introducing reactive species into the processing chamber from a clean gas that is input to a remote microwave plasma system during a second time period, with the ceramic heater heated to a second temperature of at least about 500.degree. C. during the introducing step. The method also includes cleaning surfaces in the processing chamber, with cleaning performed by the reactive species. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.