公开(公告)号：US20110237085A1

公开(公告)日：2011-09-29

申请号：US13152865

申请日：2011-06-03

申请人： FRANCIMAR CAMPANA SCHMITT ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： FRANCIMAR CAMPANA SCHMITT ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/31

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US07226876B2

公开(公告)日：2007-06-05

申请号：US11126910

申请日：2005-05-11

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US06261975B1

公开(公告)日：2001-07-17

申请号：US09262782

申请日：1999-03-04

申请人： Li-Qun Xia ,  Francimar Campana ,  Ellie Yieh

发明人： Li-Qun Xia ,  Francimar Campana ,  Ellie Yieh

IPC分类号： H01L2131

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/31629

摘要： A method for improving the reflow characteristics of a BPSG film. According to the method, a fluorine- or other halogen-doped BPSG layer is deposited over a substrate and reflowed using a rapid thermal pulse (RTP) method. The use of such an RTP reflow method results in superior reflow characteristics as compared to a 20-40 minute conventional furnace reflow process. The inventors discovered that reflowing FBPSG films in a conventional furnace may result in the highly mobile fluorine atoms diffusing from the film prior to completion of the anneal. Thus, the FBPSG layer loses the improved reflow characteristics provided by the incorporation of fluorine into the film. The RTP reflow reflows the film in a minimal amount of time (e.g., 10-90 seconds depending on the temperature used to reflow the layer and the degree of planarization required among other factors). Thus, the fluorine atoms within the FBPSG layer do not have sufficient time to migrate from the layer even if the layer is deposited over a PETEOS oxide or similar layer.

摘要翻译： 一种改善BPSG膜的回流特性的方法。 根据该方法，将氟或其它卤素掺杂的BPSG层沉积在衬底上并使用快速热脉冲（RTP）方法回流。 与20-40分钟的常规炉回流工艺相比，使用这种RTP回流方法导致优异的回流特性。 本发明人发现，在常规炉中回流FBPSG膜可能导致高度可移动的氟原子在退火完成之前从膜扩散。 因此，FBPSG层失去了通过将氟结合到膜中而提供的改进的回流特性。 RTP回流以最小的时间（例如10-90秒，取决于用于回流层的温度和其他因素所需的平坦化程度）来回流薄膜。 因此，即使该层沉积在PETEOS氧化物或类似层上，FBPSG层内的氟原子也不具有从该层迁移的足够时间。

公开(公告)号：US6153540A

公开(公告)日：2000-11-28

申请号：US34850

申请日：1998-03-04

申请人： Ishing Lou ,  Cary Ching ,  Peter W. Lee ,  Rong Pan ,  Paul Gee ,  Francimar Campana

发明人： Ishing Lou ,  Cary Ching ,  Peter W. Lee ,  Rong Pan ,  Paul Gee ,  Francimar Campana

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/31

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/31625

摘要： A method and apparatus for controlling the wet-etch rate and thickness uniformity of a dielectric layer, such as a phosphosilicate glass layer (PSG) layer. The method is based upon the discovery that the atmospheric pressure at which a PSG layer is deposited affects the wet-etch rate of the same, during a subsequent processing step, as well as the layer's thickness uniformity. As a result, the method of the present invention includes the step of pressurizing the atmospheric pressure of a semiconductor process chamber within a predetermined range after the substrate is deposited therein. Flowed into the deposition zone is a process gas comprising a silicon source, all oxygen source, and a phosphorous source; and maintaining the deposition zone at process conditions suitable for depositing a phosphosilicate glass layer on the substrate.

摘要翻译： 一种用于控制诸如磷硅酸盐玻璃层（PSG）层的介电层的湿蚀刻速率和厚度均匀性的方法和装置。 该方法基于以下发现：沉积PSG层的大气压力在随后的处理步骤期间影响其湿蚀刻速率以及层的厚度均匀性。 结果，本发明的方法包括在衬底沉积之后在预定范围内对半导体处理室的大气压进行加压的步骤。 流入沉积区的是包括硅源，全氧源和磷源的工艺气体; 以及将沉积区保持在适合于在基底上沉积磷硅酸盐玻璃层的工艺条件。

公开(公告)号：US06090206A

公开(公告)日：2000-07-18

申请号：US954299

申请日：1997-10-20

申请人： Won B. Bang ,  Matthew W. Losey ,  Francimar Campana ,  Srinivas Nemani ,  Sundar Pichai

发明人： Won B. Bang ,  Matthew W. Losey ,  Francimar Campana ,  Srinivas Nemani ,  Sundar Pichai

IPC分类号： F16K3/24 ,  C23C16/455 ,  C23C16/511 ,  F16K5/04 ,  F16K5/12 ,  F16K51/00 ,  H01L21/31 ,  C23C16/00 ,  F16K5/10

CPC分类号： F16K5/12

摘要： A throttle valve assembly is provided, including a throttle valve housing having a bore therethrough and a throttle valve plug assembly. The throttle valve plug assembly includes a shaft rotatably mounted on the throttle valve housing and a throttle valve plug having a concave cut-out portion. The throttle valve plug is mounted on the shaft within the throttle valve housing and substantially perpendicular to the bore. The throttle valve plug has at least two fully open positions and a closed position.

摘要翻译： 提供了一种节气门组件，其包括具有穿过其中的孔的节流阀壳体和节流阀插塞组件。 节流阀塞组件包括可旋转地安装在节流阀壳体上的轴和具有凹形切口部分的节流阀塞。 节气门塞被安装在节流阀壳体内的轴上且基本上垂直于孔。 节流阀塞具有至少两个完全打开位置和关闭位置。

公开(公告)号：US20090305514A1

公开(公告)日：2009-12-10

申请号：US12506954

申请日：2009-07-21

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/316 ,  H01L21/314

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US07563728B2

公开(公告)日：2009-07-21

申请号：US11678752

申请日：2007-02-26

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US07117064B2

公开(公告)日：2006-10-03

申请号：US11358793

申请日：2006-02-21

申请人： Srinivas D Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

发明人： Srinivas D Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

IPC分类号： G06F19/00 ,  C23C16/00 ,  H05H1/24 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76834 ,  C23C16/325 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  Y10S438/931

摘要： A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

公开(公告)号：US20060141805A1

公开(公告)日：2006-06-29

申请号：US11358793

申请日：2006-02-21

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76834 ,  C23C16/325 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  Y10S438/931

摘要： A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

公开(公告)号：US06913992B2

公开(公告)日：2005-07-05

申请号：US10383837

申请日：2003-03-07

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： C23C16/02 ,  C23C16/30 ,  C23C16/32 ,  C23C16/505 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。