公开(公告)号：US5963840A

公开(公告)日：1999-10-05

申请号：US748960

申请日：1996-11-13

申请人： Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

发明人： Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

IPC分类号： C23C14/00 ,  C23C16/30 ,  C23C16/40 ,  C23C16/511 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/44

CPC分类号： H01L21/31625 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02362

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US20060141805A1

公开(公告)日：2006-06-29

申请号：US11358793

申请日：2006-02-21

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76834 ,  C23C16/325 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  Y10S438/931

摘要： A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

公开(公告)号：US20050233576A1

公开(公告)日：2005-10-20

申请号：US11118678

申请日：2005-04-28

申请人： Ju-Hyung Lee ,  Ping Xu ,  Shankar Venkataraman ,  Li-Qun Xia ,  Fei Han ,  Ellie Yieh ,  Srinivas Nemani ,  Kangsub Yim ,  Farhad Moghadam ,  Ashok Sinha ,  Yi Zheng

发明人： Ju-Hyung Lee ,  Ping Xu ,  Shankar Venkataraman ,  Li-Qun Xia ,  Fei Han ,  Ellie Yieh ,  Srinivas Nemani ,  Kangsub Yim ,  Farhad Moghadam ,  Ashok Sinha ,  Yi Zheng

IPC分类号： C23C16/42 ,  C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/314

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829

摘要： Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising an oxygen-containing organosilicon compound, carbon dioxide, or combinations thereof, and an oxygen-free organosilicon compound to the processing chamber, and reacting the processing gas to deposit an oxygen-doped dielectric material on the substrate, wherein the dielectric material has an oxygen content of about 15 atomic percent or less. The oxygen-doped dielectric material may be used as a barrier layer in damascene or dual damascene applications.

公开(公告)号：US06352591B1

公开(公告)日：2002-03-05

申请号：US09613934

申请日：2000-07-11

申请人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

发明人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

IPC分类号： C23C1652

CPC分类号： C23C16/45565 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/4405 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45561 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02362 ,  H01L21/2255 ,  H01L21/31612 ,  H01L21/31625

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US06347636B1

公开(公告)日：2002-02-19

申请号：US09340602

申请日：1999-06-25

申请人： Li-Qun Xia ,  Visweswaren Sivaramakrishnan ,  Srinivas Nemani ,  Ellie Yieh ,  Gary Fong

发明人： Li-Qun Xia ,  Visweswaren Sivaramakrishnan ,  Srinivas Nemani ,  Ellie Yieh ,  Gary Fong

IPC分类号： B08B600

CPC分类号： B08B7/0035 ,  C23C16/4405 ,  H01L21/67017 ,  Y10S438/905

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US06465366B1

公开(公告)日：2002-10-15

申请号：US09660268

申请日：2000-09-12

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

IPC分类号： H01L2131

CPC分类号： H01L21/76829 ,  C23C16/325 ,  C23C16/505 ,  H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/7681

摘要： A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

摘要翻译： 公开了一种用于形成用于集成电路制造的碳化硅层的方法。 通过在电场的存在下使包含硅源，碳源和惰性气体的气体混合物反应来形成碳化硅层。 使用混频射频（RF）功率产生电场。 碳化硅层与集成电路制造工艺兼容。 在一个集成电路制造工艺中，碳化硅层用作用于制造集成电路结构的硬掩模，例如镶嵌结构。 在另一个集成电路制造工艺中，碳化硅层用作用于DUV光刻的抗反射涂层（ARC）。

公开(公告)号：US6114216A

公开(公告)日：2000-09-05

申请号：US746631

申请日：1996-11-13

申请人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

发明人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

IPC分类号： H01L21/76 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/225 ,  H01L21/31 ,  H01L21/316 ,  H01L21/762

CPC分类号： C23C16/45565 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/4405 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45561 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02362 ,  H01L21/2255 ,  H01L21/31612 ,  H01L21/31625

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US20050020048A1

公开(公告)日：2005-01-27

申请号：US10894872

申请日：2004-07-20

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

IPC分类号： C23C16/42 ,  C23C16/32 ,  H01L21/20 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L21/331

CPC分类号： H01L21/76834 ,  C23C16/325 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  Y10S438/931

摘要： A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

摘要翻译： 提供了一种形成用于集成电路制造工艺中的碳化硅层的方法。 碳化硅层通过在电场存在下使包含硅源，碳源和掺杂剂的气体混合物反应而形成。 沉积的碳化硅层具有随后期形成期间作为气体混合物中存在的掺杂剂量的函数而变化的压缩性。

公开(公告)号：US06589888B2

公开(公告)日：2003-07-08

申请号：US10238195

申请日：2002-09-09

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

IPC分类号： H01L2131

CPC分类号： H01L21/76829 ,  C23C16/325 ,  C23C16/505 ,  H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/7681

摘要： A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture of a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RE) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

摘要翻译： 公开了一种用于形成用于集成电路制造的碳化硅层的方法。 碳化硅层通过在电场存在下使硅源，碳源和惰性气体的气体混合物反应而形成。 使用混合频率射频（RE）功率产生电场。 碳化硅层与集成电路制造工艺兼容。 在一个集成电路制造工艺中，碳化硅层用作用于制造集成电路结构的硬掩模，例如镶嵌结构。 在另一个集成电路制造工艺中，碳化硅层用作用于DUV光刻的抗反射涂层（ARC）。

公开(公告)号：US06413583B1

公开(公告)日：2002-07-02

申请号：US09338470

申请日：1999-06-22

申请人： Farhad K. Moghadam ,  David W. Cheung ,  Ellie Yieh ,  Li-Qun Xia ,  Wai-Fan Yau ,  Chi-I Lang ,  Shin-Puu Jeng ,  Frederic Gaillard ,  Shankar Venkataraman ,  Srinivas Nemani

发明人： Farhad K. Moghadam ,  David W. Cheung ,  Ellie Yieh ,  Li-Qun Xia ,  Wai-Fan Yau ,  Chi-I Lang ,  Shin-Puu Jeng ,  Frederic Gaillard ,  Shankar Venkataraman ,  Srinivas Nemani

IPC分类号： C23C1640

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31053 ,  H01L21/3122 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/76828 ,  H01L21/76834

摘要： A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.

摘要翻译： 一种通过在低于约400℃的衬底温度下通过有机硅化合物和羟基形成化合物的反应沉积低介电常数的氧化硅层的方法。低介电常数膜含有残余碳并可用于间隙填充层， 预金属介电层，金属间介电层和亚微米器件中的浅沟槽隔离电介质层。 羟基化合物可以在从水或有机化合物沉积之前制备。 氧化硅层优选在低于约40℃的衬底温度下沉积到由有机硅化合物制备的衬里层上，以提供介电常数小于约3.0的间隙填充层。