公开(公告)号：US06573137B1

公开(公告)日：2003-06-03

申请号：US09603442

申请日：2000-06-23

Applicant: Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

Inventor： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Wolfgang Bergner ,  Gary B. Bronner ,  Ulrike Gruening ,  Stephan Kudelka ,  Alexander Michaelis ,  Larry Nesbit ,  Carl J. Radens ,  Till Schloesser ,  Helmut Tews

IPC: H01L218242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。 屏蔽材料沉积在存储电容器的节点导体上方。 一层硅沉积在阻挡材料上。 掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：US06559002B1

公开(公告)日：2003-05-06

申请号：US10032041

申请日：2001-12-31

Applicant: Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

Inventor： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

IPC: H01L218242

CPC classification number: H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L28/84 ,  Y10S438/964

Abstract: In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.

Abstract translation: 在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和 在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成 微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f） 使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

公开(公告)号：US06548344B1

公开(公告)日：2003-04-15

申请号：US09987956

申请日：2001-11-16

Applicant: Jochen Beintner ,  Stephan Kudelka ,  Thomas Dyer

Inventor： Jochen Beintner ,  Stephan Kudelka ,  Thomas Dyer

IPC: H01L218242

CPC classification number: H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

Abstract: In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.

Abstract translation: 在半导体结构的形成中，其中间隔物形成强烈地取决于结构（例如锥形），改善在平坦化为衬垫氮化物的多晶硅柱上的间隔物形成，其中在衬垫之前在聚氨酯的顶部上形成氧化物 氮化物条，使得在去除衬垫氮化物之后，将多晶硅回蚀刻，并且将氮化物保形共形，随后进行各向异性氮化物RIE蚀刻，使得氧化物保护下方的氮化物免受蚀刻。

公开(公告)号：US06295998B1

公开(公告)日：2001-10-02

申请号：US09318155

申请日：1999-05-25

Applicant: Stephan Kudelka ,  David Rath

Inventor： Stephan Kudelka ,  David Rath

IPC: B08B312

CPC classification number: H01L21/02052 ,  B08B3/04 ,  B08B3/12

Abstract: A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of a first deionized water portion having a predetermined concentration of the gas at a cold temperature, e.g., 20-30° C., is adjusted in a gassifier chamber having a pressure pump and a pressure sensor, to provide a predetermined under-saturated concentration of the gas at the cold temperature. The temperature of the adjusted gas concentration first water portion is then adjusted by mixing therewith a second deionized water portion having a predetermined concentration of the gas at a predetermined very hot temperature, e.g., 80° C., in a predetermined ratio in a mixer having a temperature sensor. The flows of the first and second water portions are controlled by first and second flow controllers, to form a hot bath at the hot temperature having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations. A controller is connected to the pump, pressure sensor, temperature sensor and first and second flow controllers to control the chamber pressure and the operation of the flow controllers.

Abstract translation: 提供一种系统来制备具有100％饱和浓度的气体（例如氮气）的去离子水，其在例如50-85℃的热温度和伴随的压力（例如大气压）下清洁半导体 晶片，例如硅。 在具有压力泵和压力传感器的放气室中调节在例如20-30℃的冷温度下具有预定浓度气体的第一去离子水部分的气体浓度，以提供预定的下 在低温下气体的饱和浓度。 然后通过混合具有预定浓度气体的第二去离子水部分的调节气体浓度第一水部分的温度，所述第二去离子水部分在预定的非常热的温度（例如80℃）下以预定比例在具有 温度传感器。 第一和第二水部分的流动由第一和第二流量控制器控制，以在具有这种饱和气体浓度的热温下形成热浴，以清洁晶片，例如在超声波振动下的清洗槽中。 控制器连接到泵，压力传感器，温度传感器和第一和第二流量控制器，以控制腔室压力和流量控制器的操作。

公开(公告)号：US07666752B2

公开(公告)日：2010-02-23

申请号：US11655583

申请日：2007-01-19

Applicant: Stephan Kudelka ,  Lars Oberbeck ,  Uwe Schroeder ,  Tim Boescke ,  Johannes Heitmann ,  Annette Saenger ,  Joerg Schumann ,  Elke Erben

Inventor： Stephan Kudelka ,  Lars Oberbeck ,  Uwe Schroeder ,  Tim Boescke ,  Johannes Heitmann ,  Annette Saenger ,  Joerg Schumann ,  Elke Erben

IPC: H01L21/20

CPC classification number: H01L21/02181 ,  H01G4/10 ,  H01G4/33 ,  H01L21/02189 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract translation: 本发明涉及沉积包含过渡金属化合物的电介质材料的方法。 在提供衬底之后，在衬底上依次施加包含过渡金属化合物的第一前体和主要包含水蒸汽，氨和肼中的至少一种的第二前体，形成含第一层含过渡金属的材料。 在下一步骤中，在第一层上依次施加包含臭氧和氧气中的至少一种的第一前视标和第三前标，以形成含过渡金属的材料的第二层。

公开(公告)号：US20090321805A1

公开(公告)日：2009-12-31

申请号：US12165072

申请日：2008-06-30

Applicant: Johannes von Kluge ,  Arnd Scholz ,  Joerg Radecker ,  Matthias Patz ,  Stephan Kudelka ,  Alejandro Avellan

Inventor： Johannes von Kluge ,  Arnd Scholz ,  Joerg Radecker ,  Matthias Patz ,  Stephan Kudelka ,  Alejandro Avellan

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/28 ,  H01L21/4763

CPC classification number: H01L29/4236 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621

Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.

Abstract translation: 一个实施例涉及一种集成电路，其包括布置在半导体主体中的凹槽中的导线。 绝缘材料设置在导线上。 该绝缘材料包括包括水平部分的第一绝缘层和设置在第一绝缘层上的第二绝缘层。 还公开了其它方法，装置和系统。

公开(公告)号：US20070235786A1

公开(公告)日：2007-10-11

申请号：US11399597

申请日：2006-04-07

Applicant: Christian Kapteyn ,  Stephan Kudelka

Inventor： Christian Kapteyn ,  Stephan Kudelka

IPC: H01L31/119 ,  H01L29/94 ,  H01L29/76 ,  H01L27/108

CPC classification number: H01L29/945 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/75

Abstract: A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.

Abstract translation: 特别是用于存储单元的存储电容器具有两个存储电极和布置在两个存储电极之间的电介质，中间层基本上由碳构成。

公开(公告)号：US07273790B2

公开(公告)日：2007-09-25

申请号：US10901406

申请日：2004-07-27

Applicant: Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

Inventor： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

IPC: H01L21/20

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

Abstract: Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Abstract translation: 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

公开(公告)号：US07157329B2

公开(公告)日：2007-01-02

申请号：US11053508

申请日：2005-02-08

Applicant: Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

Inventor： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC: H01L21/8234

CPC classification number: H01L27/10867 ,  H01L27/10864

Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Abstract translation: 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US20060246656A1

公开(公告)日：2006-11-02

申请号：US11115391

申请日：2005-04-27

Applicant: Stephan Kudelka ,  Guenther Aichmayr

Inventor： Stephan Kudelka ,  Guenther Aichmayr

IPC: H01L21/8242

CPC classification number: H01L27/10867

Abstract: The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact, particularly for use in a semiconductor memory cell. More specifically, the present invention relates to a manufacturing method for a trench capacitor having an isolation collar with a metal conductive fill in the collar region connected to a metal fill in the capacitor region.

Abstract translation: 本发明涉及一种具有隔离环的沟槽式电容器的制造方法，隔离环经由埋入式触点在单侧与衬底电连接，特别用于半导体存储单元。 更具体地说，本发明涉及一种用于沟槽电容器的制造方法，该沟槽电容器具有隔离套环，该隔离套环在与电容器区域中的金属填充物连接的套环区域中具有金属导电填料。