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    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation
    32.
    发明授权
    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation 有权
    半导体晶片处理方法允许器件区域在线后面（BEOL）金属布线层形成之后被选择性地退火

    公开(公告)号：US08021950B1

    公开(公告)日：2011-09-20

    申请号：US12911940

    申请日：2010-10-26

    申请人： Wagdi W. Abadeer ,  Lilian Kamal, legal representative ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    发明人： Wagdi W. Abadeer ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28044 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.

    摘要翻译： 公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。 在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。 然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。 红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。 所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。

    FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
    35.
    发明申请
    FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE 有权
    使用电影应力进行编程的保险丝链接结构和制造方法

    公开(公告)号：US20110042779A1

    公开(公告)日：2011-02-24

    申请号：US12939520

    申请日：2010-11-04

    申请人： Karl W. Barth ,  Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin S. Petrarca

    发明人： Karl W. Barth ,  Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin S. Petrarca

    IPC分类号： H01L23/525 ,  H01L29/06

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

    摘要翻译： 形成可编程熔丝结构的方法包括：在衬底中形成至少一个浅沟槽隔离（STI），在所述至少一个STI上扇形e熔丝，并在所述e熔丝上沉积层间电介质（ILD）层。 另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到 在电子熔断器的部分上方提供气隙。

    SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES
    37.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES 有权
    具有用于增强静电放电保护的基体到基底连接的半导体绝缘体器件结构以及用于这种半导体绝缘体器件结构的设计结构

    公开(公告)号：US20090256202A1

    公开(公告)日：2009-10-15

    申请号：US12102032

    申请日：2008-04-14

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L29/786

    CPC分类号： H01L27/1203 ,  H01L27/0248

    摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

    摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

    Semiconductor On-Chip Repair Scheme for Negative Bias Temperature Instability
    38.
    发明申请
    Semiconductor On-Chip Repair Scheme for Negative Bias Temperature Instability 有权
    用于负偏压温度不稳定性的半导体片上修复方案

    公开(公告)号：US20090179689A1

    公开(公告)日：2009-07-16

    申请号：US11971937

    申请日：2008-01-10

    申请人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    发明人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    IPC分类号： H03K3/42 ,  H01L21/00

    CPC分类号： H01L23/345 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

    摘要翻译： 公开了半导体芯片结构的实施例和一种对于由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件而并入局部的片上修复方案的方法。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

    SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE
    39.
    发明申请
    SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE 失效
    半导体器件散热结构

    公开(公告)号：US20090160013A1

    公开(公告)日：2009-06-25

    申请号：US11960030

    申请日：2007-12-19

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H01L29/00 ,  H01L21/4763

    CPC分类号： H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

    摘要翻译： 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。