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    MITIGATION OF DATA RETENTION DRIFT BY PROGRAMMING NEIGHBORING MEMORY CELLS
    31.
    发明申请
    MITIGATION OF DATA RETENTION DRIFT BY PROGRAMMING NEIGHBORING MEMORY CELLS 审中-公开
    通过编程相邻存储器细胞来减缓数据保留

    公开(公告)号：US20150348632A1

    公开(公告)日：2015-12-03

    申请号：US14822992

    申请日：2015-08-11

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

    Abstract translation: 一种方法包括在共享公共隔离层并存储在公共隔离层中的代表数据值的电荷量的多个存储器单元中，分配用于数据存储的第一组存储器单元，以及分配第二组 用于保护存储在第一组中的电荷的存储单元不保持漂移。 数据存储在第一组的存储单元中。 防止第一组的存储单元中保持漂移的电荷的保护量被存储在第二组的存储单元中。

    Independent management of data and parity logical block addresses
    32.
    发明授权
    Independent management of data and parity logical block addresses 有权
    独立管理数据和奇偶逻辑块地址

    公开(公告)号：US09170885B2

    公开(公告)日：2015-10-27

    申请号：US14468527

    申请日：2014-08-26

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Oren Golov ,  Naftali Sommer ,  Moshe Neerman

    IPC: G06F11/10 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06

    CPC classification number: G06F11/108 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/1096 ,  G06F12/0246 ,  G06F12/06 ,  G06F2211/1059 ,  G06F2212/7205

    Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

    Abstract translation: 数据存储方法包括在与存储在存储器中的各个逻辑地址相关联的一组数据项中识别与包含应用数据的数据项相关联的逻辑地址的第一子集，以及与包含应用数据的逻辑地址相关联的第二子集 包含已经通过应用数据计算的奇偶校验信息的数据项。 与第一识别的子集相关联的数据项存储在存储器的一个或多个第一物理存储器区域中，并且与第二识别的子集相关联的数据项存储在存储器的一个或多个第二物理存储器区域中，不同于 第一个物理内存区域。 在第一物理存储器区域和第二物理存储器区域中独立地执行存储器管理任务。

    MEMORY MULTI-CHIP PACKAGE (MCP) WITH INTEGRAL BUS SPLITTER
    35.
    发明申请
    MEMORY MULTI-CHIP PACKAGE (MCP) WITH INTEGRAL BUS SPLITTER 审中-公开
    具有集成总线分频器的存储器多芯片封装（MCP）

    公开(公告)号：US20150160890A1

    公开(公告)日：2015-06-11

    申请号：US14457237

    申请日：2014-08-12

    Applicant: Apple Inc.

    Inventor： Gil Semo ,  Asaf Bart ,  Avraham Poza Meir

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/0658 ,  G06F11/1008 ,  G06F12/0246 ,  G06F2212/7208

    Abstract: A device includes multiple memory devices, a bus splitter and a package. The bus splitter is configured to exchange storage commands and data with an external host using an external Input/Output (I/O) bus, and to distribute the storage commands and the data over multiple buses connected to respective subsets of the memory devices, so as to relay the storage commands and the data between the multiple memory devices and the external host. The memory devices and the bus splitter are contained in the package, in a multi-chip package (MCP) structure.

    Abstract translation: 设备包括多个存储设备，总线分配器和封装。 总线分配器被配置为使用外部输入/输出（I / O）总线与外部主机交换存储命令和数据，并且通过连接到存储器设备的各个子集的多个总线来分配存储命令和数据，因此 用于中继存储命令和多个存储器件与外部主机之间的数据。 存储器件和总线分配器以多芯片封装（MCP）结构包含在封装中。

    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION
    36.
    发明申请
    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 有权
    在长期静态和擦除状态下，减轻模拟记忆细胞的可靠性降低

    公开(公告)号：US20140355347A1

    公开(公告)日：2014-12-04

    申请号：US14249448

    申请日：2014-04-10

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

    IPC: G11C16/16

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。

    HINTING OF DELETED DATA FROM HOST TO STORAGE DEVICE
    38.
    发明申请
    HINTING OF DELETED DATA FROM HOST TO STORAGE DEVICE 有权
    从主机到存储设备的删除数据

    公开(公告)号：US20140156967A1

    公开(公告)日：2014-06-05

    申请号：US13693196

    申请日：2012-12-04

    Applicant: APPLE INC.

    Inventor： Avraham Poza Meir

    IPC: G06F12/02 ,  G06F12/10

    CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0649 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/10 ,  G06F17/30221

    Abstract: A storage device includes a memory and a processor. The processor is configured to store data items for a host in respective logical addresses, to identify a first subset of the logical addresses as frequently-accessed logical addresses and a second subset of the logical addresses as rarely-accessed logical addresses, to manage the frequently-accessed logical addresses separately from the rarely-accessed logical addresses, to receive from the host an indication of one or more logical addresses, which are used for storing data that is identified by the host as having been deleted by a user, and to add the logical addresses indicated by the host to the rarely-accessed logical addresses.

    Abstract translation: 存储装置包括存储器和处理器。 处理器被配置为将主机的数据项存储在相应的逻辑地址中，以将逻辑地址的第一子集识别为频繁访问的逻辑地址，并将逻辑地址的第二子集识别为很少访问的逻辑地址，以便频繁地管理 - 与很少访问的逻辑地址分开的接入的逻辑地址，以从主机接收一个或多个逻辑地址的指示，用于存储由主机识别为已被用户删除的数据的一个或多个逻辑地址，并且添加 由主机指示的逻辑地址到很少访问的逻辑地址。

    REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORY USING PARITY ZONES HAVING NEW AND OLD PARITY BLOCKS
    39.
    发明申请
    REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORY USING PARITY ZONES HAVING NEW AND OLD PARITY BLOCKS 有权
    使用具有新的和旧的奇偶性块的奇异性区域的非易失性存储器的冗余方案

    公开(公告)号：US20140129874A1

    公开(公告)日：2014-05-08

    申请号：US13670604

    申请日：2012-11-07

    Applicant: APPLE INC.

    Inventor： Etai Zaltsman ,  Julian Vlaiko ,  Ori Moshe Stern ,  Avraham Poza Meir

    IPC: G06F12/16 ,  G06F11/10

    CPC classification number: G06F11/108

    Abstract: A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.

    Abstract translation: 一种方法包括在包括多个存储器块的非易失性存储器中，定义包括至少一个旧奇偶校验块，新奇偶校验块和多个活动块的冗余区，其中一个块被定义为开放块。 将数据存储在冗余区域中，并且存储的数据被保护，使得新的输入数据被存储在开放块中，用于包括打开块的活动块的冗余信息被存储在新的奇偶校验块中，并且冗余信息用于 不包括打开块的活动块存储在旧的奇偶校验块中。 在填充开放块和新的奇偶校验块时，分配替代块用作开放块，并且新的奇偶校验块被分配用作旧的奇偶校验块。

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