公开(公告)号：US20150368796A1

公开(公告)日：2015-12-24

申请号：US14744296

申请日：2015-06-19

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Kevin JOSEPH BAUTISTA ,  Avinash SHERVEGAR ,  Yihwan KIM ,  Nyi O. MYO ,  Abhishek DUBE

IPC: C23C16/455 ,  F16L41/02

CPC classification number: C23C16/45504 ,  C23C16/24 ,  C23C16/4412 ,  C23C16/4551 ,  C23C16/45563 ,  C30B25/14 ,  C30B35/00

Abstract: Embodiments described herein generally relate to apparatus for forming silicon epitaxial layers on semiconductor devices. Deposition gases and etching gases may be provided sequentially or simultaneously to improve epitaxial layer deposition characteristics. A gas distribution assembly may be coupled to a deposition gas source and an etching gas source. Deposition gas and etching gas may remain separated until the gases are provided to a processing volume in a processing chamber. Outlets of the gas distribution assembly may be configured to provide the deposition gas and etching gas into the processing volume with varying characteristics. In one embodiment, outlets of the gas distribution assembly which deliver etching gas to the processing volume may be angled upward relative to a surface of a substrate.

Abstract translation: 本文描述的实施例一般涉及用于在半导体器件上形成硅外延层的装置。 可以顺序地或同时地提供沉积气体和蚀刻气体以改善外延层沉积特性。 气体分配组件可以耦合到沉积气体源和蚀刻气体源。 沉积气体和蚀刻气体可以保持分离，直到气体被提供到处理室中的处理体积。 气体分配组件的出口可以被配置成将沉积气体和蚀刻气体提供到具有不同特征的处理体积中。 在一个实施例中，将蚀刻气体输送到处理容积的气体分配组件的出口可以相对于衬底的表面向上倾斜。

公开(公告)号：US20240347602A1

公开(公告)日：2024-10-17

申请号：US18632003

申请日：2024-04-10

Applicant: Applied Materials, Inc.

Inventor： Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN ,  Abhishek DUBE ,  Saurabh CHOPRA

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H10B12/00

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/045 ,  H10B12/00

Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.

公开(公告)号：US20240145550A1

公开(公告)日：2024-05-02

申请号：US17975377

申请日：2022-10-27

Applicant: Applied Materials, Inc.

Inventor： Jason JEWELL ,  Abhishek DUBE

IPC: H01L29/167 ,  C23C16/24 ,  C23C16/26 ,  C23C16/52 ,  C23C16/56 ,  C30B25/16 ,  C30B29/06 ,  C30B29/68 ,  C30B33/12 ,  H01L21/02

CPC classification number: H01L29/167 ,  C23C16/24 ,  C23C16/26 ,  C23C16/52 ,  C23C16/56 ,  C30B25/16 ,  C30B29/06 ,  C30B29/68 ,  C30B33/12 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262

Abstract: A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having carrier dopants, and each cap epitaxial layer includes silicon and carbon un-doped with carrier dopants.

公开(公告)号：US20230243068A1

公开(公告)日：2023-08-03

申请号：US18131255

申请日：2023-04-05

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C. SANCHEZ ,  Mark J. SALY ,  Schubert CHU ,  Abhishek DUBE ,  Srividya NATARAJAN

IPC: C30B29/54 ,  H01L21/02 ,  C07F9/50 ,  C30B25/02 ,  H01L29/08

CPC classification number: C30B29/54 ,  H01L21/02521 ,  C07F9/5009 ,  C30B25/02 ,  H01L21/0262 ,  H01L29/0843

Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR′z, where each instance of R and each instance of R′ are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

公开(公告)号：US20220319844A1

公开(公告)日：2022-10-06

申请号：US17615877

申请日：2020-05-07

Applicant: Applied Materials, Inc.

Inventor： Chia Cheng CHIN ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Saurabh CHOPRA

IPC: H01L21/02 ,  C30B29/52 ,  C30B25/20 ,  C30B25/16 ,  C30B25/18 ,  C30B25/04 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: Generally, examples described herein relate to methods and semiconductor processing systems for anisotropically epitaxially growing a material on a silicon germanium (SiGe) surface. In an example, a surface of silicon germanium is formed on a substrate. Epitaxial silicon germanium is epitaxially grown on the surface of silicon germanium. A first growth rate of the epitaxial silicon germanium is in a first direction perpendicular to the surface of silicon germanium, and a second growth rate of the epitaxial silicon germanium is in a second direction perpendicular to the first direction. The first growth rate is at least 5 times greater than the second growth rate.

公开(公告)号：US20220093749A1

公开(公告)日：2022-03-24

申请号：US17457597

申请日：2021-12-03

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Xuebin LI ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Tushar Vidyadhar MANDREKAR ,  Yuan-hui LO ,  Patricia M. LIU ,  Sanjay NATARAJAN ,  Saurabh CHOPRA

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

公开(公告)号：US20170178962A1

公开(公告)日：2017-06-22

申请号：US15391623

申请日：2016-12-27

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Hua CHUNG ,  Jenn-Yue WANG ,  Xuebin LI ,  Yi-Chiau HUANG ,  Schubert S. CHU

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

公开(公告)号：US20160300715A1

公开(公告)日：2016-10-13

申请号：US15091332

申请日：2016-04-05

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Xuebin LI ,  Yi-Chiau HUANG ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/10

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract translation: 本公开的实施例一般涉及在增加的压力和降低的温度下在半导体器件上形成掺杂硅外延层的方法。 在一个实施例中，该方法包括将设置在处理室内的衬底加热至约550摄氏度至约800摄氏度的温度，将包含三氯硅烷（TCS），磷源和气体的硅源引入处理室 包括卤素，以及在所述衬底上沉积包含磷的含硅外延层，所述含硅外延层的磷浓度为约1×1021原子/立方厘米或更大，其中所述含硅外延层以室压力 约150托或更大。

公开(公告)号：US20160013274A1

公开(公告)日：2016-01-14

申请号：US14794914

申请日：2015-07-09

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Yihwan KIM ,  Xuebin LI

IPC: H01L29/167 ,  H01L21/3065 ,  H01L21/223 ,  H01L21/02

CPC classification number: H01L21/02579 ,  C23C16/24 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/32135

Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.

Abstract translation: 提供了在基板上形成膜的方法。 该方法包括将衬底定位在处理室的处理体积内并加热衬底。 该方法还包括通过将衬底暴露于包括硅源和卤化掺杂剂源的两种或更多种反应物来在衬底上形成半导体膜。 半导体膜包括一个或多个外延区和一个或多个非外延区。