公开(公告)号：US20200034195A1

公开(公告)日：2020-01-30

申请号：US16049216

申请日：2018-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Khaled Hamidouche ,  Bradford M. Beckmann

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Techniques for improved networking performance in systems where a graphics processing unit or other highly parallel non-central-processing-unit (referred to as an accelerated processing device or “APD” herein) has the ability to directly issue commands to a networking device such as a network interface controller (“NIC”) are disclosed. According to a first technique, the latency associated with loading certain metadata into NIC hardware memory is reduced or eliminated by pre-fetching network command queue metadata into hardware network command queue metadata slots of the NIC, thereby reducing the latency associated with fetching that metadata at a later time. A second technique involves reducing latency by prioritizing work on an APD when it is known that certain network traffic is soon to arrive over the network via a NIC.

公开(公告)号：US10209990B2

公开(公告)日：2019-02-19

申请号：US14728643

申请日：2015-06-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Wood ,  Steven K. Reinhardt ,  Bradford M. Beckmann ,  Marc S. Orr

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: A conditional fetch-and-phi operation tests a memory location to determine if the memory locations stores a specified value and, if so, modifies the value at the memory location. The conditional fetch-and-phi operation can be implemented so that it can be concurrently executed by a plurality of concurrently executing threads, such as the threads of wavefront at a GPU. To execute the conditional fetch-and-phi operation, one of the concurrently executing threads is selected to execute a compare-and-swap (CAS) operation at the memory location, while the other threads await the results. The CAS operation tests the value at the memory location and, if the CAS operation is successful, the value is passed to each of the concurrently executing threads.

公开(公告)号：US10198261B2

公开(公告)日：2019-02-05

申请号：US15096205

申请日：2016-04-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che ,  Marc S. Orr ,  Bradford M. Beckmann

IPC: G06F9/30 ,  G06F12/10 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0837 ,  G06F12/0875 ,  G06F12/0897

Abstract: A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.

公开(公告)号：US20190034151A1

公开(公告)日：2019-01-31

申请号：US15661843

申请日：2017-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Bradford M. Beckmann

IPC: G06F3/14 ,  G06T1/20 ,  G06F9/38

Abstract: A technique for implementing synchronization monitors on an accelerated processing device (“APD”) is provided. Work on an APD includes workgroups that include one or more wavefronts. All wavefronts of a workgroup execute on a single compute unit. A monitor is a synchronization construct that allows workgroups to stall until a particular condition is met. Responsive to all wavefronts of a workgroup executing a wait instruction, the monitor coordinator records the workgroup in an “entry queue.” The workgroup begins saving its state to a general APD memory and, when such saving is complete, the monitor coordinator moves the workgroup to a “condition queue.” When the condition specified by the wait instruction is met, the monitor coordinator moves the workgroup to a “ready queue,” and, when sufficient resources are available on a compute unit, the APD schedules the ready workgroup for execution on a compute unit.

公开(公告)号：US10079044B2

公开(公告)日：2018-09-18

申请号：US13721395

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Lisa R. Hsu

IPC: G06F12/00 ,  G11C5/06 ,  G06F12/02 ,  G06F12/10 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C5/06 ,  G06F12/02 ,  G06F12/10 ,  G06F13/1694 ,  G11C7/1006

Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.

公开(公告)号：US20160239302A1

公开(公告)日：2016-08-18

申请号：US14682971

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Bradford M. Beckmann ,  Dmitri Yudanov

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46

Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.

Abstract translation: 提出了一种方法，非暂时计算机可读介质和用于在处理单元上的程序代码执行期间重新包装动态波前的处理器，每个动态波前包括多个线程。 如果检测到分支指令，则确定程序代码中跟随相同控制路径的所有波前是否已经到达作为分支指令的压缩点。 如果在执行程序代码时没有检测到分支指令，则确定跟随相同控制路径的所有波前是否已经达到重新收敛点，该再失真点是要由执行分支而不是执行的程序代码段的开始 从前一个分支指令中分支。 如果跟随相同控制路径的所有波前已经到达分支指令或再聚合点，那么动态波前将重新打包所有遵循相同控制路径的线程。

公开(公告)号：US09189399B2

公开(公告)日：2015-11-17

申请号：US13887196

申请日：2013-05-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1036 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/6032 ,  G06F2212/683 ,  G06F2212/684 ,  Y02B60/1225 ,  Y02D10/13

Abstract: A processor system presented here has a plurality of execution cores and a plurality of stack caches, wherein each of the stack caches is associated with a different one of the execution cores. A method of managing stack data for the processor system is presented here. The method maintains a stack cache manager for the plurality of execution cores. The stack cache manager includes entries for stack data accessed by the plurality of execution cores. The method processes, for a requesting execution core of the plurality of execution cores, a virtual address for requested stack data. The method continues by accessing the stack cache manager to search for an entry of the stack cache manager that includes the virtual address for requested stack data, and using information in the entry to retrieve the requested stack data.

Abstract translation: 这里呈现的处理器系统具有多个执行内核和多个堆栈高速缓存，其中每个堆栈高速缓存与不同的执行核心相关联。 此处介绍了处理器系统的堆栈数据管理方法。 该方法维护多个执行核心的堆栈高速缓存管理器。 堆栈缓存管理器包括由多个执行核心访问的堆栈数据的条目。 该方法对于多个执行核心的请求执行核心处理所请求的堆栈数据的虚拟地址。 该方法通过访问堆栈高速缓存管理器来继续搜索包括所请求的堆栈数据的虚拟地址的堆栈高速缓存管理器的条目，并使用条目中的信息来检索所请求的堆栈数据。

公开(公告)号：US20150058567A1

公开(公告)日：2015-02-26

申请号：US14010096

申请日：2013-08-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Blake A. Hechtman ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  Y02D10/13

Abstract: A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.

Abstract translation: 描述了一种方法，计算机程序产品和系统，其强制与特殊访问顺序一致（RCsc）存储器模型的版本一致性，并且执行诸如StRel事件之类的释放同步指令，而不通过存储器层次来跟踪未完成的存储事件，同时有效地使用 带宽资源。 还描述了存储事件与存储事件的顺序相对于RCsc存储器模型的去耦。 该描述还包括一组分层只读缓存和只写组合缓冲器，其将来自系统的不同部分的存储合并。 此外，池组件维护接收到的存储事件的部分顺序并释放同步事件，以避免内容可寻址存储器（CAM）结构，全缓存刷新以及对存储器的直接写入。 该方法提高了全局和本地同步事件的性能，并降低了维持只写组合缓冲区的开销。

公开(公告)号：US20140250442A1

公开(公告)日：2014-09-04

申请号：US13782063

申请日：2013-03-01

Applicant: ADVANCED MICRO DEVICES, INC

Inventor： Steven K. Reinhardt ,  Marc S. Orr ,  Bradford M. Beckmann

IPC: G06F9/54

CPC classification number: G06F9/542 ,  G06F2209/543

Abstract: The described embodiments include a computing device. In these embodiments, an entity in the computing device receives an identification of a memory location and a condition to be met by a value in the memory location. Upon a predetermined event occurring, the entity causes an operation to be performed when the value in the memory location meets the condition.

Abstract translation: 所描述的实施例包括计算设备。 在这些实施例中，计算设备中的实体通过存储器位置中的值接收存储器位置的标识和要满足的条件。 当预定事件发生时，当存储器位置中的值满足条件时，实体导致执行操作。

公开(公告)号：US20140181417A1

公开(公告)日：2014-06-26

申请号：US13726146

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  Lisa R. Hsu ,  Michael Ignatowski ,  Michael J. Schulte

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G11C5/025 ,  G11C8/12 ,  G11C29/12 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  Y02D10/13 ,  H01L2924/00

Abstract: A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.

Abstract translation: 堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。 一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。 存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。 相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。 由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。