公开(公告)号：US11830817B2

公开(公告)日：2023-11-28

申请号：US17085215

申请日：2020-10-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Rahul Agarwal ,  Raja Swaminathan ,  Michael S. Alfano ,  Gabriel H. Loh ,  Alan D. Smith ,  Gabriel Wong ,  Michael Mantor

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

公开(公告)号：US11360891B2

公开(公告)日：2022-06-14

申请号：US16355168

申请日：2019-03-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/0802 ,  G06F12/084 ,  G06F12/0846

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

公开(公告)号：US20220091980A1

公开(公告)日：2022-03-24

申请号：US17031706

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Yasuko Eckert ,  Mark Henry Oskin ,  Gabriel H. Loh ,  Steven E. Raasch ,  Maxim V. Kazakov

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0877 ,  G06F13/16 ,  G06F11/30

Abstract: A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.

公开(公告)号：US20200343236A1

公开(公告)日：2020-10-29

申请号：US16927111

申请日：2020-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/433

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20200257796A1

公开(公告)日：2020-08-13

申请号：US16857058

申请日：2020-04-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Maurice B. Steinman

IPC: G06F21/55 ,  H04L29/06 ,  G06F21/71

Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.

公开(公告)号：US10282295B1

公开(公告)日：2019-05-07

申请号：US15825880

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  Michael W. Boyer ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.

公开(公告)号：US10158712B2

公开(公告)日：2018-12-18

申请号：US14730837

申请日：2015-06-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Eric Christopher Morton

IPC: G06F15/16 ,  H04L29/08 ,  G06F3/06

Abstract: A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node. The technique may include determining the memory request efficiency indicators based on comparisons of target addresses of the memory requests to addresses of recent memory requests of the first node.

公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US09825843B2

公开(公告)日：2017-11-21

申请号：US14715023

申请日：2015-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H01L25/065 ,  H01L23/498 ,  H04L12/755 ,  G06F17/50 ,  H01L23/48 ,  H01L23/538 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

公开(公告)号：US20170277639A1

公开(公告)日：2017-09-28

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/683

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.