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    Storing incidental branch predictions to reduce latency of misprediction recovery
    31.
    发明授权
    Storing incidental branch predictions to reduce latency of misprediction recovery 有权

    公开(公告)号：US12204908B2

    公开(公告)日：2025-01-21

    申请号：US15997344

    申请日：2018-06-04

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Douglas Williams ,  Ashok T. Venkatachar ,  Sudherssen Kalaiselvan

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.

    Selectively performing ahead branch prediction based on types of branch instructions
    35.
    发明授权
    Selectively performing ahead branch prediction based on types of branch instructions 有权

    公开(公告)号：US11416256B2

    公开(公告)日：2022-08-16

    申请号：US16945275

    申请日：2020-07-31

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Aparna Thyagarajan ,  Ashok T. Venkatachar

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/355 ,  G06F9/35

    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

    Using loop exit prediction to accelerate or suppress loop mode of a processor
    36.
    发明授权
    Using loop exit prediction to accelerate or suppress loop mode of a processor 有权

    公开(公告)号：US11256505B2

    公开(公告)日：2022-02-22

    申请号：US17169053

    申请日：2021-02-05

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Arunachalam Annamalai ,  Marius Evers ,  Aparna Thyagarajan ,  Anthony Jarvis

    IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

    Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

    SCHEDULER QUEUE ASSIGNMENT BURST MODE
    37.
    发明申请
    SCHEDULER QUEUE ASSIGNMENT BURST MODE 有权

    公开(公告)号：US20210173702A1

    公开(公告)日：2021-06-10

    申请号：US16709527

    申请日：2019-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alok Garg ,  Scott Andrew McLelland ,  Marius Evers ,  Matthew T. Sobel

    IPC: G06F9/48

    Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment burst mode are disclosed. A scheduler queue assignment unit receives a dispatch packet with a plurality of operations from a decode unit in each clock cycle. The scheduler queue assignment unit determines if the number of operations in the dispatch packet for any class of operations is greater than a corresponding threshold for dispatching to the scheduler queues in a single cycle. If the number of operations for a given class is greater than the corresponding threshold, and if a burst mode counter is less than a burst mode window threshold, the scheduler queue assignment unit dispatches the extra number of operations for the given class in a single cycle. By operating in burst mode for a given operation class during a small number of cycles, processor throughput can be increased without starving the processor of other operation classes.

    Taint protection during speculative execution
    38.
    发明授权
    Taint protection during speculative execution 有权

    公开(公告)号：US10956157B1

    公开(公告)日：2021-03-23

    申请号：US16293154

    申请日：2019-03-05

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David Kaplan ,  Marius Evers

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A subset of a set of architectural registers in a processing system is marked (or “tainted”) to indicate that speculative use of data in the subset of the architectural registers is constrained based on a taint handling policy. One or more speculation features supported by the processing system are disabled for the instruction so that the one or more speculation features cannot be used on data in the subset. In some cases, values of bits associated with the subset of architectural registers are modified to indicate that the subset is tainted. The taint handling policy can be indicated by values stored in a policy register. Taint markings are tracked in response to values stored in the tainted architectural registers being written to a memory or read from the memory.

    Dynamic evaluation and reconfiguration of a data prefetcher
    39.
    发明授权
    Dynamic evaluation and reconfiguration of a data prefetcher 有权
    数据预取器的动态评估和重新配置

    公开(公告)号：US09058277B2

    公开(公告)日：2015-06-16

    申请号：US13671801

    申请日：2012-11-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sharad Dilip Bade ,  Alok Garg ,  John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

    IPC: G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0862 ,  G06F9/3842 ,  G06F11/30 ,  G06F2212/6024 ,  G06F2212/6026 ,  Y02D10/13

    Abstract: Methods and systems for prefetching data for a processor are provided. A system is configured for and a method includes selecting one of a first prefetching control logic and a second prefetching control logic of the processor as a candidate feature, capturing the performance metric of the processor over an inactive sample period when the candidate feature is inactive, capturing a performance metric of the processor over an active sample period when the candidate feature is active, comparing the performance metric of the processor for the active and inactive sample periods, and setting a status of the candidate feature as enabled when the performance metric in the active period indicates improvement over the performance metric in the inactive period, and as disabled when the performance metric in the inactive period indicates improvement over the performance metric in the active period.

    Abstract translation: 提供了用于为处理器预取数据的方法和系统。 系统被配置用于并且方法包括选择处理器的第一预取控制逻辑和第二预取控制逻辑之一作为候选特征，当候选特征不活动时，在非活动采样周期捕获处理器的性能度量， 当候选特征处于活动状态时，在活动采样周期捕获处理器的性能度量，比较处于活动和非活动采样周期的处理器的性能度量，并且将候选特征的状态设置为使能时的性能度量 活动期间表示在非活动期间的性能指标改善，当非活动期间的性能指标表示改善了活动期间的绩效指标时被禁用。

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