Fuel cell
    31.
    发明授权
    Fuel cell 失效
    燃料电池

    公开(公告)号:US5364711A

    公开(公告)日:1994-11-15

    申请号:US41427

    申请日:1993-03-31

    摘要: In a fuel cell comprising a stack having superposed a plurality of electromotive parts composed of a fuel electrode, an oxidizing electrode, and an electrolyte layer nipped by the two electrodes and using a liquid fuel as the fuel for the fuel cell, this invention contemplates forming a liquid fuel introducing path destined to be directly exposed to the liquid fuel on terminal surfaces of the component parts of the electromotive parts in a direction perpendicular to the flow of an oxidizing gas along at least one of the outer peripheral surfaces of the stack including the terminal surface of the fuel electrode and lying parallelly to the flow of the oxidizing gas and enabling the liquid fuel in the liquid fuel introducing path to be supplied to the fuel electrodes by a capillary attraction. A fuel cell provided with means for recovery of the water produced by the cell reaction in the oxidizing electrodes is also disclosed, which fuel cell effects the removal of the water produced in the oxidizing electrodes during the operation of the fuel cell by a capillary attraction generated by two porous members.

    摘要翻译: 在包括由燃料电极,氧化电极和由两个电极夹持并且使用液体燃料作为燃料电池的燃料的电解质层组成的多个电动部分叠置的燃料电池中,本发明考虑到形成 液体燃料导入路径,其特征在于,所述液体燃料导入路径旨在直接暴露于所述电动部件的所述构成部件的端子面的液体燃料,所述液体燃料导向路径沿与所述氧化气体的流动方向垂直的方向沿着所述堆叠体的至少一个外周面, 燃料电极的端子表面并且与氧化气体的流动平行地放置,并且能够通过毛细吸引力将液体燃料引入路径中的液体燃料供应到燃料电极。 还公开了一种燃料电池,其具有用于回收由氧化电极中的电池反应产生的水的装置,该燃料电池通过产生毛细管吸引力而在燃料电池的操作期间实现氧化电极中产生的水的去除 由两个多孔构件。

    Method of making a read only memory device
    33.
    发明授权
    Method of making a read only memory device 失效
    制作只读存储器件的方法

    公开(公告)号:US4904615A

    公开(公告)日:1990-02-27

    申请号:US301978

    申请日:1989-01-26

    IPC分类号: H01L27/112 H01L21/8246

    CPC分类号: H01L27/1126

    摘要: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

    PRESSURIZED WATER REACTOR
    34.
    发明申请
    PRESSURIZED WATER REACTOR 有权
    加压水反应器

    公开(公告)号:US20130343505A1

    公开(公告)日:2013-12-26

    申请号:US13993227

    申请日:2011-12-13

    IPC分类号: G21C15/02

    摘要: The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).

    摘要翻译: 根据一个实施方案的加压水反应器包括:连接入口喷嘴的圆柱形反应器压力容器(1); 包含在反应堆压力容器(1)内的燃料组件; 围绕燃料组件并在反应堆芯筒(3)和反应堆压力容器(1)的内表面之间形成环形降液管(6)的圆柱形反应堆芯筒(3); 和径向支撑。 径向支撑件是沿圆周方向间隔地设置在降液管(6)下方的支撑件,每个都具有形成在其中的垂直流动通道,并且将反应堆堆芯筒(3)和反应堆压力容器(1)定位。 径向支撑件各自具有例如具有流动路径的径向键(21)和键槽构件(40)。

    Semiconductor device and manufacturing method of same
    35.
    发明授权
    Semiconductor device and manufacturing method of same 有权
    半导体器件及其制造方法

    公开(公告)号:US08399926B2

    公开(公告)日:2013-03-19

    申请号:US13283264

    申请日:2011-10-27

    IPC分类号: H01L27/12

    摘要: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

    摘要翻译: 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管,以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET,形成在衬底上部的矩形固体半导体层,具有平行于衬底的主平面的顶表面和垂直于衬底的(100)面的侧面 基板的主平面,形成在矩形半导体层中的沟道区,至少形成在矩形层的侧面上的栅极绝缘膜,栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区, 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

    RANDOM NUMBER GENERATION DEVICE
    36.
    发明申请
    RANDOM NUMBER GENERATION DEVICE 审中-公开
    随机数生成装置

    公开(公告)号:US20090309646A1

    公开(公告)日:2009-12-17

    申请号:US12391640

    申请日:2009-02-24

    IPC分类号: G06G7/12 H01L27/088

    摘要: A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.

    摘要翻译: 随机数生成装置包括:第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。 第一绝缘膜具有陷阱捕获和释放电荷,并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。

    SEMICONDUCTOR DEVICE
    37.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20080054346A1

    公开(公告)日:2008-03-06

    申请号:US11846830

    申请日:2007-08-29

    IPC分类号: H01L29/792

    摘要: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

    摘要翻译: 公开了一种半导体器件,其能够通过实现大的阈值电压偏移和长的保持时间来实现低电压驱动性和大的存储容量(小型化),同时抑制存储器单元之间的特性的变化。 该器件包括半导体存储单元,其具有形成在半导体衬底中的沟道区,沟道区上的隧道绝缘膜,隧道绝缘膜上的电荷存储绝缘膜,电荷存储膜上的控制电介质膜,控制电极 在控制电介质膜上,以及在沟道区的相对端处的源/漏区。 存储单元的沟道区域具有与沿着沟道长度的方向成直角的横截面,其宽度W和高度H都小于或等于10nm。

    Logic apparatus and logic circuit
    38.
    发明授权

    公开(公告)号:US07138651B2

    公开(公告)日:2006-11-21

    申请号:US10893916

    申请日:2004-07-20

    IPC分类号: H01L29/06

    摘要: A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

    Static random access memory
    39.
    发明申请
    Static random access memory 失效
    静态随机存取存储器

    公开(公告)号:US20050062071A1

    公开(公告)日:2005-03-24

    申请号:US10909399

    申请日:2004-08-03

    摘要: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.

    摘要翻译: 静态随机存取存储器具有第一和第二互补场效应晶体管。 第一互补场效应晶体管包括半导体衬底,具有构成肖特基结的第一漏区和栅极的电子传导型的第一场效应晶体管和正空穴传导型的第一场效应晶体管, 共享第一漏极区域并具有共用栅电极。 第二互补场效应晶体管包括具有第二漏极区和栅极的电子传导型的第二场效应晶体管,共享第二漏极区并具有共享的空穴导体型的第二场效应晶体管 栅电极。 由第一和第二互补场效应晶体管共享的栅电极连接到相互相对的互补场效应晶体管的公共漏区,并且静态随机存取存储器具有优异的软件误差抵抗能力。