公开(公告)号：US20050095820A1

公开(公告)日：2005-05-05

申请号：US10862518

申请日：2004-06-07

申请人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

发明人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L29/66628 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665

摘要： The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

摘要翻译： 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其它实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：US20050093075A1

公开(公告)日：2005-05-05

申请号：US10974232

申请日：2004-10-27

申请人： Ralf Bentum ,  Scott Luning ,  Andy Wei

发明人： Ralf Bentum ,  Scott Luning ,  Andy Wei

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66628 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78687

摘要： By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

摘要翻译： 通过优选通过半导体层的局部氧化来凹入半导体层，可以通过随后的外延生长工艺在栅极电极结构附近的薄化半导体层中引入应力诱导材料和/或掺杂物种类。 特别地，与栅电极结构相邻形成的应力诱导材料根据所沉积材料的类型施加压缩或拉伸应力，从而也增强了晶体管元件的沟道区中电荷载流子的迁移率。

公开(公告)号：US20050009285A1

公开(公告)日：2005-01-13

申请号：US10915638

申请日：2004-08-09

申请人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

发明人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

摘要： An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

摘要翻译： 一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。 栅极结构（112）形成在半导体衬底（102）的主表面（104）上。 在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。 使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。 源极（132）和漏极（134）区域形成在半导体衬底（102）中。 在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。 电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

公开(公告)号：US06355528B1

公开(公告)日：2002-03-12

申请号：US09426911

申请日：1999-10-26

申请人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

发明人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

摘要： A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

摘要翻译： 在衬底上形成窄槽。 为了形成这样的窄槽，在基板上形成第一材料，第一材料具有侧壁。 形成邻接侧壁的间隔物。 随后，与间隔物相邻地形成第二材料。 去除间隔物，留下第一材料和第二材料之间的凹槽。 在一个实施例中，槽被填充用于诸如门的窄特征的材料，并且第一材料和第二材料被去除。 结果，形成具有由间隔物的宽度限定的长度的门或其他窄特征。 在另一个实施例中，通过小凹槽执行植入物，导致小的局部植入物。

公开(公告)号：US5639691A

公开(公告)日：1997-06-17

申请号：US590781

申请日：1996-01-24

申请人： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

发明人： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

公开(公告)号：US5626967A

公开(公告)日：1997-05-06

申请号：US452589

申请日：1995-05-25

申请人： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

发明人： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/06

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/32137

摘要： A structure for patterning a polysilicon layer includes a TiN layer located above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is located above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

摘要翻译： 用于图案化多晶硅层的结构包括位于形成TiN / a-Si叠层的非晶硅（a-Si）层之上的TiN层。 TiN / a-Si堆叠位于多晶硅层上方。 TiN层用作ARC以减少用于图案化多晶硅层的光刻胶的过度曝光，而a-Si层防止多晶硅层下面的层的污染。

公开(公告)号：US08912603B2

公开(公告)日：2014-12-16

申请号：US13180300

申请日：2011-07-11

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US08039349B2

公开(公告)日：2011-10-18

申请号：US12512814

申请日：2009-07-30

申请人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

发明人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

IPC分类号： H01L21/8234

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785

摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

摘要翻译： 提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。 在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分 结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

公开(公告)号：US07977174B2

公开(公告)日：2011-07-12

申请号：US12480269

申请日：2009-06-08

申请人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

发明人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

IPC分类号： H01L21/00

CPC分类号： H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

摘要翻译： 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和门结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

公开(公告)号：US07960229B2

公开(公告)日：2011-06-14

申请号：US12100598

申请日：2008-04-10

申请人： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

发明人： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

摘要： A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

摘要翻译： 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。