公开(公告)号：US07381622B2

公开(公告)日：2008-06-03

申请号：US11559462

申请日：2006-11-14

申请人： Andreas Hellmich ,  Gunter Grasshoff ,  Fernando Koch ,  Andy Wei ,  Thorsten Kammler

发明人： Andreas Hellmich ,  Gunter Grasshoff ,  Fernando Koch ,  Andy Wei ,  Thorsten Kammler

IPC分类号： H01L21/338 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L29/66628 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

摘要翻译： 通过图案化间隔层堆叠并在原位蚀刻工艺中蚀刻空腔，可以显着增强在嵌入的应变半导体层的形成期间的工艺复杂性以及均匀性。 在初始阶段中，间隔层堆叠可以在具有高度均匀性的各向异性蚀刻步骤的基础上进行图案化，因为可能不需要各个层叠层之间的选择性。 此后，可以进行清洁处理，然后进行腔蚀刻工艺，其中在间隔物图案化过程期间减少的过度蚀刻时间显着有助于最终获得的空腔的均匀性，而工艺的原位性质也提供了减少的 整个处理时间。

公开(公告)号：US20080102590A1

公开(公告)日：2008-05-01

申请号：US11750816

申请日：2007-05-18

申请人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

发明人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

IPC分类号： H01L21/336 ,  H01L21/428

CPC分类号： H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

公开(公告)号：US07344984B2

公开(公告)日：2008-03-18

申请号：US11468450

申请日：2006-08-30

申请人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

发明人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。

公开(公告)号：US20080023692A1

公开(公告)日：2008-01-31

申请号：US11688946

申请日：2007-03-21

申请人： Frank Wirbeleit ,  Andy Wei ,  Roman Boschke

发明人： Frank Wirbeleit ,  Andy Wei ,  Roman Boschke

IPC分类号： H01L31/00 ,  H01L29/06

CPC分类号： H01L29/105 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.

摘要翻译： 通过在栅极图案化之前在硅基有源半导体区域中形成半导体合金，除了其应变诱导效应之外，还可以利用半导体合金本身的材料特性。 因此，与在漏极和源极区域中使用应变半导体合金的常规方法相比，先进的场效应晶体管的器件性能可以进一步提高。

公开(公告)号：US20070252144A1

公开(公告)日：2007-11-01

申请号：US11567268

申请日：2006-12-06

申请人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

发明人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

IPC分类号： H01L31/00

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

摘要翻译： 通过相对于硅层的结晶特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料的应力诱导效应可以显着提高。 在一个说明性实施例中，通道可以沿着（100）表面取向沿着<100>方向取向，从而提供大约四分之一的电子迁移率增加。

公开(公告)号：US20070232006A1

公开(公告)日：2007-10-04

申请号：US11559462

申请日：2006-11-14

申请人： Andreas Hellmich ,  Gunter Grasshoff ,  Fernando Koch ,  Andy Wei ,  Thorsten Kammler

发明人： Andreas Hellmich ,  Gunter Grasshoff ,  Fernando Koch ,  Andy Wei ,  Thorsten Kammler

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

摘要翻译： 通过图案化间隔层堆叠并在原位蚀刻工艺中蚀刻空腔，可以显着增强在嵌入的应变半导体层的形成期间的工艺复杂性以及均匀性。 在初始阶段中，间隔层堆叠可以在具有高度均匀性的各向异性蚀刻步骤的基础上进行图案化，因为可能不需要各个层叠层之间的选择性。 此后，可以进行清洁处理，然后进行腔蚀刻工艺，其中在间隔物图案化过程期间减少的过度蚀刻时间显着有助于最终获得的空腔的均匀性，而工艺的原位性质也提供了减少的 整个处理时间。

公开(公告)号：US20070202653A1

公开(公告)日：2007-08-30

申请号：US11550941

申请日：2006-10-19

申请人： Jan Hoentschel ,  Andy Wei ,  Gert Burbach ,  Peter Javorka

发明人： Jan Hoentschel ,  Andy Wei ,  Gert Burbach ,  Peter Javorka

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/26506 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78621

摘要： By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

摘要翻译： 通过使用一次性间隔物方法在非晶化过程之前形成漏极和源极区域，以在存在应力间隔层的情况下重新结晶半导体区域，可能与增强的退火技术（例如激光和闪光退火工艺）结合， 可以提供更有效的应变产生机构。 此外，用于形成金属硅化物的间隔物可以具有减小的宽度，从而将相应的金属硅化物区域更靠近沟道区域。 因此，可以基于上述技术获得总体增强的性能。

公开(公告)号：US20060113629A1

公开(公告)日：2006-06-01

申请号：US11177214

申请日：2005-07-08

申请人： Andy Wei ,  Thorsten Kammler ,  Michael Raab ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Michael Raab ,  Manfred Horstmann

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76254 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659

摘要： By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

摘要翻译： 通过直接键合具有不同晶体取向和/或材料组成和/或内部应变的两个晶体半导体层，可以形成块状混合衬底，从而提供根据混合物上的单晶体管结构形成半导体器件的潜力 基质。

公开(公告)号：US08580643B2

公开(公告)日：2013-11-12

申请号：US13217009

申请日：2011-08-24

申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886

摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

摘要翻译： 当在共同制造顺序中形成复杂的多个栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US08298924B2

公开(公告)日：2012-10-30

申请号：US11866491

申请日：2007-10-03

申请人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

发明人： Maciej Wiatr ,  Frank Wirbeleit ,  Andy Wei ,  Andreas Gehring

IPC分类号： H01L27/092 ,  H01L21/04

CPC分类号： H01L21/823864 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的晶体管元件的外部间隔物，在形成金属硅化物之前，采用湿化学蚀刻工艺，可以将应力接触衬垫层更靠近 从而允许用于在沟道区域中产生相应应变的高效应力传递机构，而不影响P型区域中的电路元件。