公开(公告)号：US5880502A

公开(公告)日：1999-03-09

申请号：US709425

申请日：1996-09-06

Applicant: John K. Lee ,  Behnam Moradi ,  Michael J. Westphal

Inventor： John K. Lee ,  Behnam Moradi ,  Michael J. Westphal

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L21/82385 ,  H01L27/0922 ,  H01L29/1087 ,  H01L29/4916 ,  H01L29/7835

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

公开(公告)号：US07824994B2

公开(公告)日：2010-11-02

申请号：US12271132

申请日：2008-11-14

Applicant: Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

Inventor： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20090068812A1

公开(公告)日：2009-03-12

申请号：US12271132

申请日：2008-11-14

Applicant: Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

Inventor： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US07492086B1

公开(公告)日：2009-02-17

申请号：US09489286

申请日：2000-01-21

Applicant: David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

Inventor： David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

IPC: H01J1/02 ,  H01J63/04

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter comprises an electropositive element both in a body of the emitter and on a surface of the emitter. According to another aspect of the invention, a process for manufacturing a FED is provided comprising the steps of forming an emitter comprising an electropositive element in the body of the tip; positioning the emitter in opposing relation to a phosphor display screen; creating an evacuated space between the emitter tip and the phosphor display screen; and causing the electropositive element to migrate to an emission surface of the emitter.

Abstract translation: 根据本发明的一个方面，提供一种场发射显示器，包括：阳极; 位于阳极上的荧光屏; 阴极 阳极和阴极之间的抽空空间; 位于与磷光体相对的阴极上的发射极; 其中所述发射器包括在所述发射体的主体和所述发射极的表面上的正电极元件。 根据本发明的另一方面，提供了一种用于制造FED的方法，包括以下步骤：在所述尖端的主体中形成包含正电荷元件的发射器; 将发射器定位成与荧光体显示屏相对的关系; 在发射极尖端和荧光体显示屏之间产生抽空空间; 并使正电荷元件迁移到发射极的发射表面。

公开(公告)号：US20060278913A1

公开(公告)日：2006-12-14

申请号：US11147976

申请日：2005-06-08

Applicant: Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

Inventor： Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

IPC: H01L29/788 ,  H01L21/336 ,  G11C16/04

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n-layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.

Abstract translation: 多个存储单元堆叠形成在衬底上。 衬底在每个存储单元堆之间不具有扩散区，以连接存储单元。 电池形成得足够接近，使得存储器单元由通道区域中的每个浮动栅极产生的电场串联连接。 在一个实施例中，在衬底的顶部注入n层以增加电池之间的导电性。 选择晶体管可以通过扩散区域或通过选择晶体管沟道和存储单元通道之间的电场的相互作用而连接到串行串。

公开(公告)号：US06515414B1

公开(公告)日：2003-02-04

申请号：US09564356

申请日：2000-05-01

Applicant: David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

Inventor： David A. Cathey ,  Surjit S. Chadha ,  Behnam Moradi

IPC: H01J162

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter comprises an electropositive element both in a body of the emitter and on a surface of the emitter. According to another aspect of the invention a process for manufacturing an FED is provided comprising the steps of: forming an emitter comprising an electropositive element in the body of the tip; positioning the emitter in opposing relation to a phosphor display screen; creating an evacuated space between the emitter tip and the phosphor display screen; and causing the electropositive element to migrate to the an emission surface of the emitter.

Abstract translation: 根据本发明的一个方面，提供一种场发射显示器，包括：阳极; 位于阳极上的荧光屏; 阴极 阳极和阴极之间的抽空空间; 位于与磷光体相对的阴极上的发射极; 其中所述发射器包括在所述发射体的主体和所述发射极的表面上的正电极元件。 根据本发明的另一方面，提供了一种用于制造FED的方法，包括以下步骤：在尖端的主体中形成包含正电荷元件的发射器; 将发射器定位成与荧光体显示屏相对的关系; 在发射极尖端和荧光体显示屏之间产生抽空空间; 并使正电荷元件迁移到发射体的发射表面。

公开(公告)号：US06509686B1

公开(公告)日：2003-01-21

申请号：US09398155

申请日：1999-09-16

Applicant: Behnam Moradi ,  Kanwal K. Raina ,  Michael J. Westphal

Inventor： Behnam Moradi ,  Kanwal K. Raina ,  Michael J. Westphal

IPC: H01J1304

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.

Abstract translation: 改进的场致发射显示器包括位于阴极组件中的铬栅电极和相关介电层之间的铜，铝，氮化硅或掺杂或未掺杂的非晶，多晶或微晶硅的缓冲层。 缓冲层基本上减少或消除了铬栅电极和电介质层之间的不利的化学反应的发生。

公开(公告)号：US06436788B1

公开(公告)日：2002-08-20

申请号：US09126695

申请日：1998-07-30

Applicant: John K. Lee ,  Behnam Moradi

Inventor： John K. Lee ,  Behnam Moradi

IPC: H01L2176

CPC classification number: H01J3/022

Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid. This reduces distortion in field emission displays.

公开(公告)号：US06323587B1

公开(公告)日：2001-11-27

申请号：US09130634

申请日：1998-08-06

Applicant: Tianhong Zhang ,  John K. Lee ,  Behnam Moradi

Inventor： Tianhong Zhang ,  John K. Lee ,  Behnam Moradi

IPC: H01J130

CPC classification number: H01J9/025 ,  H01J1/3044 ,  H01J2201/30446

Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.

Abstract translation: 场致发射显示装置包括形成在基板上的多个发射体。 每个发射器包括硅化钛氮化物外层，使得发射体不易劣化。 在基板和发射体上形成电介质层，并且在围绕每个发射体的电介质层中形成开口。 导电提取栅格基本上在由发射器限定的平面中形成在介质层上，并且包括围绕每个发射器的开口。 具有平坦表面的阴极发光面板平行于基板设置。

公开(公告)号：US06271632B1

公开(公告)日：2001-08-07

申请号：US09621948

申请日：2000-07-24

Applicant: John K. Lee ,  Behnam Moradi

Inventor： John K. Lee ,  Behnam Moradi

IPC: H01J130

CPC classification number: H01J3/022

Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid. This reduces distortion in field emission displays.

Abstract translation: 描述了一种发射器子结构及其制造方法。 衬底具有形成在衬底的表面上的p区。 形成n型罐，使得p型区域围绕n型罐的周边。 发射极形成在n电池上并电耦合到n型电池。 在基板上形成介电层，该介质层包括围绕发射极的开口。 在电介质层上形成提取栅格。 提取格栅包括围绕并且紧邻发射器的尖端的开口。 在n型罐的下边界处形成绝缘区域。 绝缘区域沿着开口下方的下边界的至少一部分电隔离发射极和n坦克。 因此，绝缘区域用于从可以由穿过提取栅格中的光子或提取栅格中的开口的光子照射的区域移位与p区域和n坦克之间的边界相关联的耗尽区域。 这减少了场致发射显示器的失真。