公开(公告)号：US06348373B1

公开(公告)日：2002-02-19

申请号：US09538017

申请日：2000-03-29

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: H01L218242

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/31155 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/517

Abstract: A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.

Abstract translation: 通过沉积初始膜和注入氧离子以改善膜的氧缺陷，同时减少或消除界面二氧化硅层的形成来改善高介电常数膜的电性能的方法。 初始高介电常数材料通过CVD，反应溅射或蒸发沉积在硅衬底上。 尽管还提供了其他方法，但优选使用等离子体离子浸渍（PIII）来注入氧离子。 在注入后，将衬底退火以调节高介电常数膜。

公开(公告)号：US6060755A

公开(公告)日：2000-05-09

申请号：US356470

申请日：1999-07-19

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: C23C14/08 ,  C23C14/14 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56 ,  H01B3/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8232 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L28/56

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Abstract translation: 提供了一种高k电介质膜，其在相对高的退火温度下保持非晶态。 高k电介质膜是掺杂有三价金属如Al的Zr或Hf的金属氧化物。 由于膜抵抗晶体结构的形成，与相邻膜的界面具有较少的不规则性。 当用作栅极电介质时，可以使膜变薄以支持更小的晶体管几何形状，同时沟道区域的表面可以被制成平滑的以支持高电子迁移率。 还提供了用于上述三价金属掺杂的高介电膜的CVD，溅射和蒸发沉积方法。

公开(公告)号：US08661652B1

公开(公告)日：2014-03-04

申请号：US13456653

申请日：2012-04-26

Applicant: Ronald L. Koepp ,  Ronald A. Oliver ,  William T. Colleran ,  Yanjun Ma ,  Jay M. Fassett ,  Vincent C. Moretti

Inventor： Ronald L. Koepp ,  Ronald A. Oliver ,  William T. Colleran ,  Yanjun Ma ,  Jay M. Fassett ,  Vincent C. Moretti

IPC: H01P11/00

CPC classification number: H01Q23/00 ,  G06K19/07756 ,  H01Q1/2208

Abstract: RFID tags are assembled through affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.

Abstract translation: RFID标签通过将天线和IC的电容器与电容器的电介质材料形成一个或多个电容器组成，该电容器包括IC的非导电覆盖层，非集成电路 天线的导电覆盖层，例如氧化物层，和/或另外形成的电介质层。 电容器的顶板和底板由天线迹线和IC顶表面上的一个或多个贴片形成。

公开(公告)号：US20110298051A1

公开(公告)日：2011-12-08

申请号：US13214044

申请日：2011-08-19

Applicant: Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

Inventor： Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

IPC: H01L27/06 ,  H01L29/778

CPC classification number: H01L27/0251

Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。 这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域 与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作 源极或漏极区。 公开了附加装置，系统和方法。

公开(公告)号：US08022498B1

公开(公告)日：2011-09-20

申请号：US11837810

申请日：2007-08-13

Applicant: Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

Inventor： Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

IPC: H01L29/00

CPC classification number: H01L27/0251

Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。 这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域 与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作 源极或漏极区。 公开了附加装置，系统和方法。

公开(公告)号：US07732887B2

公开(公告)日：2010-06-08

申请号：US11387603

申请日：2006-03-22

Applicant: Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

Inventor： Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

IPC: H01L31/07

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Abstract translation: 具有改进性能的肖特基结二极管器件是在常规CMOS工艺中制造的。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括掺杂到与第一导电类型相反的第二导电类型的材料。 含金属材料的区域设置在第一阱之上，以在含金属材料区域和第一阱之间的界面处形成肖特基结。 在一个实施例中，第一井接触设置在第一井的一部分中。 第二阱设置在衬底上，其中第二阱包括掺杂到第一导电类型的材料。 在一个实施例中，第一井和第二井不彼此直接接触。

公开(公告)号：US07679957B2

公开(公告)日：2010-03-16

申请号：US11106982

申请日：2005-04-15

Applicant: Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

Inventor： Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

IPC: G11C16/06

CPC classification number: G11C29/789 ,  G11C29/76

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

Abstract translation: 两个浮置栅极器件以非易失性存储器（NVM）中的冗余配置布置，使得应力诱发的漏电流（SILC）或其他故障不会导致存储器存储的完全丢失。 冗余NVM可以被布置为串联配置，并行配置，单端设备，差分设备，简单逻辑电路功能，复杂逻辑电路功能和/或作为RFID标签系统的一部分。

公开(公告)号：US07482251B1

公开(公告)日：2009-01-27

申请号：US11891392

申请日：2007-08-09

Applicant: Ronald E Paulsen ,  Ronald L. Koepp ,  Yanjun Ma ,  Larry Morrell ,  Andrew E. Horch

Inventor： Ronald E Paulsen ,  Ronald L. Koepp ,  Yanjun Ma ,  Larry Morrell ,  Andrew E. Horch

IPC: H01L21/00 ,  H01L21/44

CPC classification number: H01L21/78

Abstract: Methods are provided, and devices made by such methods. One of the methods includes procuring a semiconductor wafer, processing the wafer to form a plurality of circuits on a top side, forming trenches on the top side between the adjacent circuits, forming a trench passivation layer on side walls of the trenches, forming conductive bumps on the top side of the wafer; and removing material from the bottom side to thin the wafer, and eventually separate the wafer along the trenches into dies, where each die includes only one of the circuits.

Abstract translation: 提供方法，以及通过这些方法制造的装置。 其中一种方法包括采购半导体晶片，处理晶片以在顶侧形成多个电路，在相邻电路之间的顶侧上形成沟槽，在沟槽的侧壁上形成沟槽钝化层，形成导电凸块 在晶片的顶面; 并且从底侧去除材料以使晶片细化，并且最终将晶片沿着沟槽分离成模具，其中每个管芯仅包括一个电路。

公开(公告)号：US06503763B2

公开(公告)日：2003-01-07

申请号：US09819879

申请日：2001-03-27

Applicant: Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

Inventor： Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

IPC: H01L2100

CPC classification number: H01L21/28291 ,  H01L29/516 ,  H01L29/78391

Abstract: A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

Abstract translation: 用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口， 设备的可靠性。

公开(公告)号：US06184157B2

公开(公告)日：2001-02-06

申请号：US09088456

申请日：1998-06-01

Applicant: Sheng Teng Hsu ,  Hongning Yang ,  David R. Evans ,  Tue Nguyen ,  Yanjun Ma

Inventor： Sheng Teng Hsu ,  Hongning Yang ,  David R. Evans ,  Tue Nguyen ,  Yanjun Ma

IPC: B05D306

CPC classification number: C23C14/50 ,  C23C14/06 ,  C23C14/22 ,  C23C16/30 ,  C23C16/44 ,  C23C16/4582

Abstract: A method has been provided to counteract the inherent tension in a deposited film. A wafer substrate is fixed to a wafer chuck having a curved surface. When the chuck surface is convex, a tensile stress is implanted in a deposited film. Upon release from the chuck, the deposited film develops a compressive stress. When the chuck surface is concave, a compressive stress is implanted in the deposited film. Upon release from the chuck, the deposited film develops a tensile stress. Loading a film with a compressive stress is helpful in making films having an inherently tensile stress become thermal stable. Stress loading is also used to improve adhesion between films, and to prevent warping of a film during annealing. A product-by-process using the above-described method is also provided.

Abstract translation: 已经提供了一种抵消沉积膜中的固有张力的方法。 将晶片基板固定到具有弯曲表面的晶片卡盘。 当卡盘表面凸出时，在沉积膜中注入拉伸应力。 当从卡盘释放时，沉积的膜产生压缩应力。 当卡盘表面凹陷时，在沉积膜中注入压应力。 当从卡盘释放时，沉积的膜产生拉伸应力。 加载具有压应力的薄膜有助于使具有固有拉伸应力的薄膜变得热稳定。 应力负荷也用于提高膜之间的粘附性，并且防止退火期间膜的翘曲。 还提供了使用上述方法的逐个方法。