公开(公告)号：US20050153485A1

公开(公告)日：2005-07-14

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/335

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。

公开(公告)号：US20050121716A1

公开(公告)日：2005-06-09

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06876042B1

公开(公告)日：2005-04-05

申请号：US10653105

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A FinFET includes a fin formed on an insulating layer and a first gate material layer formed proximate to sides of the fin. The FinFET further includes a protective layer formed above the first gate material layer and the fin, and a second gate material layer formed above the protective layer and the fin. The second gate material layer may be formed into a gate for the fin that may be biased independently of gate(s) formed from the first gate material layer, thus providing additional design flexibility in controlling the potential in the fin during on/off switching of the FinFET.

Abstract translation: FinFET包括形成在绝缘层上的鳍和靠近鳍的侧面形成的第一栅极材料层。 FinFET还包括形成在第一栅极材料层和鳍上方的保护层，以及形成在保护层和鳍上方的第二栅极材料层。 第二栅极材料层可以形成为可以独立于由第一栅极材料层形成的栅极偏置的鳍的栅极，从而在控制鳍的电位的开/关切换期间提供额外的设计灵活性 FinFET。

公开(公告)号：US06855607B2

公开(公告)日：2005-02-15

申请号：US10459495

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

公开(公告)号：US06787439B2

公开(公告)日：2004-09-07

申请号：US10290276

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构。 翅片结构可以包括侧表面和顶表面。 该方法还可以包括在鳍结构上沉积栅极材料并平坦化沉积的栅极材料。 可以在平坦化的栅极材料上沉积抗反射涂层，并且可以使用抗反射涂层从平坦化栅极材料形成栅极结构。

公开(公告)号：US06764884B1

公开(公告)日：2004-07-20

申请号：US10405342

申请日：2003-04-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method of manufacturing a FinFET device includes forming a fin structure on an insulating layer. The fin structure includes a conductive fin. The method also includes forming source/drain regions and forming a dummy gate over the fin. The dummy gate may be removed and the width of the fin in the channel region may be reduced. The method further includes depositing a gate material to replace the removed dummy gate.

Abstract translation: 制造FinFET器件的方法包括在绝缘层上形成翅片结构。 翅片结构包括导电翅片。 该方法还包括形成源极/漏极区域并在鳍片上形成虚拟栅极。 可以去除伪栅极，并且可以减小沟道区域中的鳍的宽度。 该方法还包括沉积栅极材料以取代去除的虚拟栅极。

公开(公告)号：US06686231B1

公开(公告)日：2004-02-03

申请号：US10310777

申请日：2002-12-06

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在翅片结构的沟道部分上形成栅极结构。 该方法还可以包括在栅极结构周围形成牺牲氧化物层并去除栅极结构以在牺牲氧化物层内限定栅极凹槽。 可以在栅极凹部中形成金属栅极，并且可以去除牺牲氧化物层。

公开(公告)号：US08008136B2

公开(公告)日：2011-08-30

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US07541267B1

公开(公告)日：2009-06-02

申请号：US11765611

申请日：2007-06-20

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/28

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract translation: 一种方法包括从半导体材料层形成第一矩形台面并在第一台面周围形成第一介电层。 该方法还包括在第一台面的第一部分上形成第一矩形掩模，离开第一台面的暴露的第二部分并蚀刻第一台面的暴露的第二部分以从第一台面产生反向的T形翅片。

公开(公告)号：US07262104B1

公开(公告)日：2007-08-28

申请号：US10857931

申请日：2004-06-02

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.

Abstract translation: 形成具有不同阈值电压的多个半导体器件。 根据一个示例性实施例，第一和第二半导体器件被形成和掺杂不同，导致第一和第二半导体器件的不同阈值电压。