公开(公告)号：US20170186623A1

公开(公告)日：2017-06-29

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas POSSEME ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/447 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/324 ,  H01L21/02057 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/447 ,  H01L21/762 ,  H01L21/823468 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7827

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US20170154826A1

公开(公告)日：2017-06-01

申请号：US15361260

申请日：2016-11-25

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Maxime GARCIA-BARROS

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/823864 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823468 ,  H01L28/00 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78654

Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate; depositing a layer comprising carbon, said layer being disposed distant from said transistor; modifying the protective layer to form a modified protective layer; forming a protective film on the layer comprising carbon; removing the protective film on surfaces of the protective film that are perpendicular to a main implantation direction; selectively removing the layer comprising carbon; and at least one step of selectively removing the modified protective layer.

公开(公告)号：US20150270163A1

公开(公告)日：2015-09-24

申请号：US14661371

申请日：2015-03-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME

IPC: H01L21/768 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method for producing interconnection lines including etching a layer of porous dielectric material forming a trench and filling the trench is provided. The etching is carried out in a plasma so as to grow, all along the etching, a protective layer on flanks of the layer of porous dielectric material. The plasma is formed from a gas formed from a first component and a second component, or a gas formed from a first component, a second component and a third component. The first component is a hydrocarbon of the CXHY type, where X is the proportion of carbon in the gas and Y the proportion of hydrogen in the gas; the second component is taken from nitrogen or dioxygen or a mixture of nitrogen and dioxygen; the third component is taken from argon or helium; and the protective layer is based on hydrocarbon.

Abstract translation: 提供了一种制造互连线的方法，包括蚀刻形成沟槽并填充沟槽的多孔介电材料层。 蚀刻在等离子体中进行，以便沿着蚀刻生长在多孔介电材料层的侧面上的保护层。 等离子体由由第一组分和第二组分形成的气体或由第一组分，第二组分和第三组分形成的气体形成。 第一组分是CXHY型烃，其中X是气体中碳的比例，Y是气体中氢的比例; 第二组分取自氮或二氧或氮和二氧的混合物; 第三组分取自氩或氦; 并且保护层基于烃。

公开(公告)号：US20220352344A1

公开(公告)日：2022-11-03

申请号：US17730459

申请日：2022-04-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Valentin BACQUIE

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115

Abstract: A method for forming spacers of a gate of a transistor is provided, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions, and basal portions covering the active layer; anisotropically modifying the basal portions by implantation of hydrogen-based ions in a direction parallel to the lateral sides of the gate, forming modified basal portions; annealing desorbing the hydrogen from the active layer and transforming the modified basal portions into second modified basal portions; and removing the modified basal portions by selective etching of the modified dielectric material with respect to the non-modified dielectric material and with respect to the semiconductive material, so as to form the spacers on the lateral sides of the gate.

公开(公告)号：US20220068653A1

公开(公告)日：2022-03-03

申请号：US17446723

申请日：2021-09-02

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Simon RUEL

IPC: H01L21/3065 ,  H01L29/205 ,  H01J37/32

Abstract: A method for etching at least one portion of a III-N material layer, including the implementation of the following steps of: a) first etching of a first part of the thickness of the portion of the III-N material layer, implemented by using a first plasma including chlorine; b) exposing at least one part of a remaining thickness of the portion of the III-N material layer to a second plasma including helium or hydrogen; c) chlorinating the part of the remaining thickness of the portion of the III-N material layer, transforming the part of the remaining thickness of the portion of the III-N material layer into a chlorinated material layer; d) second etching of the chlorinated material layer, implemented by using a third plasma including argon.

公开(公告)号：US20210090880A1

公开(公告)日：2021-03-25

申请号：US17018204

申请日：2020-09-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Frédéric LE ROUX

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265

Abstract: A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.

公开(公告)号：US20210057283A1

公开(公告)日：2021-02-25

申请号：US16999642

申请日：2020-08-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762

Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.

公开(公告)号：US20200335327A1

公开(公告)日：2020-10-22

申请号：US16304969

申请日：2017-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Raluca TIRON ,  Nicolas POSSEME ,  Xavier CHEVALIER

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115

Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.

公开(公告)号：US20200251569A1

公开(公告)日：2020-08-06

申请号：US16722246

申请日：2019-12-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/02

Abstract: There is provided a method for producing a transistor with a raised source and drain the method including depositing a layer on the gate pattern and the active layer; carrying out an isotropic modification of the layer over a thickness to obtain a first portion of modified layer, carrying out an anisotropic modification of the layer over another thickness, along a direction normal to the active layer, to obtain second portions of modified layer, by conserving portions of non-modified layer on the flanks of the gate pattern and at the foot of the gate pattern, removing the first and second modified portions by conserving the portions, by selective etching, to form spacers having an L-shape, epitaxially growing the source and drain in contact with the L-shaped spacers, to obtain the source and drain having tilted faces.

公开(公告)号：US20200185497A1

公开(公告)日：2020-06-11

申请号：US16699384

申请日：2019-11-29

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas POSSEME ,  Louis HUTIN ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI

IPC: H01L29/12 ,  H01L29/417 ,  H03K17/567

Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.