Abstract:
A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.
Abstract:
A nonvolatile semiconductor memory device and a method of fabricating the same are provided. The nonvolatile memory device may include a switching device and a storage node connected to the switching device. The storage node may comprise a lower electrode, a data storing layer, and an upper electrode. The data storing layer may include a first region where a current path is formed at a first voltage, and a second region surrounding the first region where a current path is formed at a second voltage, greater than the first voltage. The first region may be positioned to contact the upper electrode and the lower electrode.
Abstract:
A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.
Abstract:
Provided are a method of growing carbon nanotubes and a carbon nanotube device. The method includes: depositing an aluminum layer on a substrate; forming an insulating layer over the substrate to cover the aluminum layer; patterning the insulating layer and the aluminum layer on the substrate to expose a side of the aluminum layer; forming a plurality of holes in the exposed side of the aluminum layer to a predetermined depth; depositing a catalyst metal layer on the bottoms of the holes; and growing the carbon nanotubes from the catalyst metal layer.
Abstract:
A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.
Abstract:
A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.
Abstract:
An electron emission lithography apparatus and method using a selectively grown carbon nanotube as an electron emission source, wherein the electron emission lithography apparatus includes an electron emission source installed within a chamber and a stage, which is separated from the electron emission source by a predetermined distance and on which a sample is mounted, and wherein the electron emission source is a carbon nanotube having electron emission power. Since a carbon nanotube is used as an electron emission source, a lithography process can be performed with a precise critical dimension that prevents a deviation from occurring between the center of a substrate and the edge thereof and may realize a high throughput.
Abstract:
A ferroelectric read and write memory of a nondestructive write and read (NDWR) method in which charges of a gate insulating layer induced by a ferroelectric capacitor are discharged via a separate path, includes a source and a drain provided in both side of a well; a gate insulating layer provided on the well; a gate electrode provided on the gate insulating layer; a ferroelectric layer provided on the gate electrode, to which corresponding charges are induced in the gate electrode depending on its polar states; an upper electrode provided on the ferroelectric layer; and a charge discharging means electrically connected to the gate electrode for discharging charges induced in the gate insulating layer. In a driving method thereof, charges of the gate insulating layer induced by the ferroelectric layer are directly discharged via the gate electrode to make a logic "low" state by blocking the current flow between the source and insulating layer through the well during a binary logic information write operation. Therefore, if the information is written in a non-inversion state of the polarization, a fatigue of the ferroelectric layer can be prevented. Also, as described above, since the remained polarization still exists during the repeated information write operations, the information can be written at a low voltage.
Abstract:
A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.
Abstract:
The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.