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    Method of forming a gate overlap LDD structure
    31.
    发明授权
    Method of forming a gate overlap LDD structure 失效
    形成栅极重叠LDD结构的方法

    公开(公告)号：US5304504A

    公开(公告)日：1994-04-19

    申请号：US71563

    申请日：1993-06-02

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： B01D61/02 ,  B01D61/08 ,  B01D61/12 ,  H01L21/265

    CPC分类号： B01D61/025 ,  B01D61/08 ,  B01D61/12

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Gate overlapping LDD structure
    32.
    发明授权
    Gate overlapping LDD structure 失效
    门重叠LDD结构

    公开(公告)号：US5276347A

    公开(公告)日：1994-01-04

    申请号：US809398

    申请日：1991-12-18

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/7836

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Method of making oxide-isolated source/drain transistor
    34.
    发明授权
    Method of making oxide-isolated source/drain transistor 失效
    制造氧化物隔离源/漏晶体管的方法

    公开(公告)号：US4963502A

    公开(公告)日：1990-10-16

    申请号：US416566

    申请日：1989-10-03

    申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

    CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928

    摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

    摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些“源极/漏极”区域36通过使用硅蚀刻形成凹部，用氧化物衬在蚀刻的凹槽上，以及 回填多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的扩散部分44，其作为电有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

    Definition of anti-fuse cell for programmable gate array application
    37.
    发明授权
    Definition of anti-fuse cell for programmable gate array application 有权
    用于可编程门阵列应用的反熔丝单元的定义

    公开(公告)号：US06307248B1

    公开(公告)日：2001-10-23

    申请号：US09289890

    申请日：1999-04-12

    申请人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

    发明人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

    IPC分类号： H01L2900

    CPC分类号： H01L27/11803 ,  Y10S438/922

    摘要： A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

    摘要翻译： 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。

    Method of forming an integrated circuit device
    38.
    发明授权
    Method of forming an integrated circuit device 失效
    形成集成电路器件的方法

    公开(公告)号：US6027979A

    公开(公告)日：2000-02-22

    申请号：US73417

    申请日：1998-05-06

    申请人： Che-Chia Wei

    发明人： Che-Chia Wei

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/6659

    摘要： A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

    摘要翻译： 掩模用于集成电路器件中的轻掺杂漏极和光晕注入。 掩模只露出与场效应晶体管栅电极相邻的衬底的部分。 由于光晕植入仅在晶体管通道附近进行，在其中它执行有用的功能，因此获得了足够的器件可靠性和性能。 由于从不需要的有源区的那些部分掩盖光晕注入，所以有源区域结电容降低。 这种降低的电容导致提高的晶体管切换速度。 用于限定轻掺杂的漏极和晕圈注入区域的掩模可以容易地由已经存在的栅极和有源区域几何形状的直接组合形成。

    Semiconductor contact metallization
    40.
    发明授权
    Semiconductor contact metallization 失效
    半导体接触金属化

    公开(公告)号：US5677238A

    公开(公告)日：1997-10-14

    申请号：US638667

    申请日：1996-04-29

    申请人： Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

    发明人： Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/283

    CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843

    摘要： A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

    摘要翻译： 已经开发了用于制造硅中的有源器件区域与覆盖金属化水平之间的改进连接的方法。 该方法产生具有优异和改善的屏障完整性的触点，其允许硅器件暴露于延长的热处理时间和/或较高温度过程，而不会金属渗入硅接触接合区域。 关键元素是在多层阻挡结构中添加共形CVD钨层。