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104 条记录 (耗时 0.036 秒)

    Structure and method for self aligned vertical plate capacitor
    38.
    发明授权
    Structure and method for self aligned vertical plate capacitor 失效
    自对准立板电容器的结构和方法

    公开(公告)号：US07670921B2

    公开(公告)日：2010-03-02

    申请号：US11616955

    申请日：2006-12-28

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

    IPC分类号： H01L21/4763

    CPC分类号： H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

    摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

    摘要翻译： 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图和保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

    Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance
    39.
    发明授权
    Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance 有权
    具有背面触点的半导体器件结构，用于改善散热和降低的寄生电阻

    公开(公告)号：US07622357B2

    公开(公告)日：2009-11-24

    申请号：US11420282

    申请日：2006-05-25

    申请人： Kunal Vaed ,  Jae-Sung Rieh ,  Richard P. Volant ,  Francois Pagette

    发明人： Kunal Vaed ,  Jae-Sung Rieh ,  Richard P. Volant ,  Francois Pagette

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7371 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.

    摘要翻译： 本发明涉及一种器件结构，其包括具有前表面和后表面的衬底，以及至少一个具有位于衬底中的第一导电结构的半导体器件和位于其上的第二导电结构。 第一导电接触位于衬底的前表面上并且横向偏离第一导电结构。 第一导电接触件通过导电路径电连接到第一导电结构，导电路径延伸：（1）从第一导电结构通过基底延伸到背面，（2）延伸穿过后表面，和（3）从背面 通过基板的表面到前表面上的第一导电接触。 此外，第二导电触点位于前表面上并且电连接到第二导电结构。 导电路径可以通过光刻和蚀刻形成，之后是金属沉积。

    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems
    40.
    发明授权
    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems 失效
    微机电系统的准确高效的质量和可靠性评估装置

    公开(公告)号：US07602265B2

    公开(公告)日：2009-10-13

    申请号：US11163485

    申请日：2005-10-20

    申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

    摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。