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公开(公告)号：US20090111229A1
公开(公告)日：2009-04-30
申请号：US11931376
申请日：2007-10-31
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译： 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。
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公开(公告)号：US20090111226A1
公开(公告)日：2009-04-30
申请号：US11926348
申请日：2007-10-29
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11534 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.
摘要翻译： 提供了一种用于将非易失性存储器（NVM）电路与逻辑电路集成的方法。 该方法包括在NVM区域和衬底的逻辑区域上沉积第一层栅极材料层。 该方法还包括沉积包括彼此叠置的氮化物，氧化物和氮化物（ARC层）的多个邻接的牺牲层。 多个相邻的牺牲层用于在NVM区域中对存储晶体管的选择栅极和控制栅极进行图案化，并且多个相邻牺牲层的ARC层用于在逻辑区域中对逻辑晶体管的栅极进行图案化。
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33.发明授权Process for operating an electronic device including a memory array and conductive lines 有权用于操作包括存储器阵列和导线的电子设备的工艺公开(公告)号：US07262997B2
公开(公告)日：2007-08-28
申请号：US11188898
申请日：2005-07-25
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。
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公开(公告)号：US07091130B1
公开(公告)日：2006-08-15
申请号：US10876820
申请日：2004-06-25
IPC分类号： H01I21/302
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。
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35.发明授权Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor 有权具有具有不同密度的纳米晶体的不同非易失性存储器的半导体器件及其方法公开(公告)号：US08679912B2
公开(公告)日：2014-03-25
申请号：US13362697
申请日：2012-01-31
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。
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公开(公告)号：US08178406B2
公开(公告)日：2012-05-15
申请号：US11926323
申请日：2007-10-29
IPC分类号： H01L27/088 , H01L27/108
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L29/1037 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66636 , H01L29/66659
摘要： A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the first sidewall of the select gate. The thin layer of charge storage material is formed in which a first portion of the thin layer of charge storage material is formed in the first recess and a second portion of the thin layer of charge storage material is formed along the first sidewall of the first select gate. The control gate is formed over the first portion of the thin layer of charge storage material. The result is a semiconductor device useful a memory cell.
摘要翻译： 在半导体层上制造半导体器件的方法包括形成选择栅极，凹槽，电荷存储层和控制栅极。 选择栅极形成在半导体层上方具有第一侧壁。 凹槽形成在与选择栅极的第一侧壁相邻的半导体层中。 形成电荷存储材料的薄层，其中电荷存储材料薄层的第一部分形成在第一凹槽中，并且电荷存储材料薄层的第二部分沿着第一选择的第一侧壁形成 门。 控制栅极形成在电荷存储材料薄层的第一部分上。 结果是用于存储单元的半导体器件。
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公开(公告)号：US08035156B2
公开(公告)日：2011-10-11
申请号：US12241786
申请日：2008-09-30
IPC分类号： H01L29/792 , H01L21/8246 , H01L21/336
CPC分类号： H01L29/66833 , H01L29/42328 , H01L29/42344 , H01L29/66537 , H01L29/66636 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.
摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 选择栅极结构形成在衬底上。 控制栅结构具有侧壁。 在与侧壁相邻的区域中的衬底上形成外延层。 在外延层上形成电荷存储层。 在电荷存储层上形成控制栅极。 这允许在选择栅极下的原位掺杂外延层而不需要反掺杂。 避免反掺杂是有益的，因为反掺杂降低了电荷迁移率并增加了控制阈值电压的难度。 此外，可以在衬底中形成凹部，并且在凹部中形成外延层，并且可以在形成外延层之前通过凹槽进入在选择栅极下方的区域中的衬底中的晕圈注入。
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公开(公告)号：US20100128537A1
公开(公告)日：2010-05-27
申请号：US12277404
申请日：2008-11-25
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/10 , G11C16/349
摘要： A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.
摘要翻译： 包括非易失性存储单元的存储器系统。 存储器系统包括基于存储器系统的单元已经被擦除的次数将单元编程为第一阈值电压或第二阈值电压的程序电路。 在一个实施例中，当存储器系统的任何一组单元已被擦除特定次数时，阈值电压被降低。
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公开(公告)号：US07622349B2
公开(公告)日：2009-11-24
申请号：US11302937
申请日：2005-12-14
IPC分类号： H01L21/8239 , H01L21/28
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/7881
摘要： A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.
摘要翻译： 提供了一种方法，其包括形成覆盖在电子器件基板的主表面上的第一栅极并且形成覆盖并与第一栅极间隔开的第二栅极。 该方法还包括形成电荷存储结构，该电荷存储结构沿着第一栅极和第二栅极水平相邻并连续地延伸，其中电荷存储结构的主表面基本上垂直于衬底的主表面。
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40.发明授权Non-volatile memory device with improved data retention and method therefor 有权具有改进的数据保留的非易失性存储器件及其方法公开(公告)号：US07432547B2
公开(公告)日：2008-10-07
申请号：US10779004
申请日：2004-02-13
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/42324 , H01L29/511 , H01L29/518 , H01L29/792
摘要： A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
摘要翻译： 半导体器件（30）包括下层绝缘层（34），上覆绝缘层（42）和在绝缘层（34,42）之间的电荷存储层（36）。 电荷存储层（36）和上覆绝缘层（42）形成存储电荷存储层（36）中至少大部分电荷的界面。 这可以通过在一个实施例中通过形成具有不同材料的电荷存储层（36）来实现，例如硅和硅锗层或n型和p型材料层。 在另一个实施例中，电荷存储层（36）包括分级的掺杂剂。 通过在电荷存储层（36）和上覆绝缘层（42）之间的界面处存储至少大部分电荷，通过下面的绝缘层的电荷泄漏减小，允许更薄的下层绝缘层（34） 要使用的。
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