利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

146 条记录 (耗时 0.042 秒)

    PCM with poly-emitter BJT access devices
    31.
    发明授权
    PCM with poly-emitter BJT access devices 有权
    PCM与多发射器BJT接入设备

    公开(公告)号：US08138574B2

    公开(公告)日：2012-03-20

    申请号：US12510588

    申请日：2009-07-28

    申请人： Tze-Chiang Chen ,  Chung Hon Lam ,  Bipin Rajendran

    发明人： Tze-Chiang Chen ,  Chung Hon Lam ,  Bipin Rajendran

    IPC分类号： H01L27/06

    CPC分类号： H01L45/1233 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06

    摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.

    摘要翻译： 相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。 用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

    Multi-bit memory error detection and correction system and method
    32.
    发明授权
    Multi-bit memory error detection and correction system and method 有权
    多位存储器错误检测和校正系统及方法

    公开(公告)号：US08055988B2

    公开(公告)日：2011-11-08

    申请号：US11694025

    申请日：2007-03-30

    申请人： Chung Hon Lam

    发明人： Chung Hon Lam

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G06F11/1072 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C27/005 ,  G11C29/00 ,  G11C2211/5641

    摘要： A system and method for operating a collection of memory cells includes storing binary data values and parity data values by associating binary values with a common adjustable characteristic parameter of a memory cell collection. Probability distribution functions for values of the characteristic parameter of the memory cell collection are read and constructed. Binary data values and parity data values stored in the memory cell collection are retrieved. Parity data for error detection and error correction is evaluated in the binary data values.

    摘要翻译： 用于操作存储器单元的集合的系统和方法包括通过将二进制值与存储器单元集合的公共可调特性参数相关联来存储二进制数据值和奇偶校验数据值。 对存储单元集合的特性参数的值的概率分布函数进行读取和构造。 检索存储在存储单元集合中的​​二进制数据值和奇偶校验数据值。 用于错误检测和纠错的奇偶校验数据在二进制数据值中进行评估。

    Current constricting phase change memory element structure
    33.
    发明授权
    Current constricting phase change memory element structure 有权
    电流限制相变存储元件结构

    公开(公告)号：US07932507B2

    公开(公告)日：2011-04-26

    申请号：US12727672

    申请日：2010-03-19

    申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

    IPC分类号： H01L29/02

    CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

    摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

    Phase change memory cell with vertical transistor
    34.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    Fill-in etching free pore device
    36.
    发明授权
    Fill-in etching free pore device 有权
    填充蚀刻自由孔装置

    公开(公告)号：US07879645B2

    公开(公告)日：2011-02-01

    申请号：US12020717

    申请日：2008-01-28

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

    IPC分类号： H01L21/06 ,  H01L21/44

    CPC分类号： H01L45/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L21/76808 ,  H01L21/76816 ,  H01L27/222 ,  H01L27/24 ,  H01L43/08 ,  H01L45/145

    摘要： A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

    摘要翻译： 存储单元包括在底部电极层上方具有第一介电层的存储单元层，在第一介电层上的第二电介质层和位于第二介电层上的顶部电极。 电介质层限定具有由第一电极层和底部电极限定的第一部分和由第二电介质层和顶部电极限定的第二部分的通孔。 存储元件位于通孔内并与顶部和底部电极电接触。 通孔的第一和第二部分可以分别包括收缩的能量集中区和扩大区。 收缩区域可以具有小于用于形成通孔的扩大区域的过程的最小特征尺寸的宽度。 还公开了一种用于制造存储单元的方法。

    ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK
    39.
    发明申请
    ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK 审中-公开
    由共聚物掩模定义的电极中形成的电极

    公开(公告)号：US20090239334A1

    公开(公告)日：2009-09-24

    申请号：US12052581

    申请日：2008-03-20

    申请人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

    IPC分类号： H01L21/00

    CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material.

    摘要翻译： 提供了一种制造存储器件的方法，其在一个实施例中包括提供包括含有存储材料的第一通孔的层间介电层; 在所述存储材料和所述层间电介质层的上表面上形成至少一个绝缘层; 通过所述至少一个绝缘层的厚度的一部分形成空腔; 在至少所述空腔中形成共聚物掩模，所述共聚物掩模包括至少一个开口，所述至少一个开口提供覆盖所述存储材料的所述至少一个绝缘层的剩余部分的暴露表面; 蚀刻所述至少一个绝缘层的剩余部分的暴露表面以向所述存储材料提供第二通孔; 以及在所述第二通孔内与所述记忆材料电接触形成导电材料。