公开(公告)号：US20060105582A1

公开(公告)日：2006-05-18

申请号：US11250439

申请日：2005-10-17

申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.

摘要翻译： 提供了一种方法：在硅衬底的表面上排列氮原子; 在氢气氛中进行热处理，使得存在于硅衬底表面上的氮原子和硅原子处于三配位键状态; 并且在硅衬底上形成具有氮原子的三配位键状态并保持硅原子的氧化硅膜。

公开(公告)号：US20060097287A1

公开(公告)日：2006-05-11

申请号：US11319534

申请日：2005-12-29

申请人： Ichiro Mizushima

发明人： Ichiro Mizushima

IPC分类号： H01L29/94 ,  H01L21/8244

CPC分类号： H01L27/10894 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10897

摘要： A semiconductor device of this invention comprises a semiconductor substrate, a plurality of memory regions provided on the semiconductor substrate, the plurality of memory regions having the same structure, and functional region provided on the semiconductor substrate, the functional region including a different function from the memory.

摘要翻译： 本发明的半导体器件包括半导体衬底，设置在半导体衬底上的多个存储区域，具有相同结构的多个存储区域和设置在半导体衬底上的功能区域，功能区域包括与 记忆。

公开(公告)号：US20050242397A1

公开(公告)日：2005-11-03

申请号：US11168914

申请日：2005-06-29

申请人： Hajime Nagano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Ichiro Mizushima

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/01 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

公开(公告)号：US06956265B2

公开(公告)日：2005-10-18

申请号：US10675950

申请日：2003-10-02

申请人： Hajime Nagano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Ichiro Mizushima

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/01 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

摘要翻译： 封闭半导体器件，其包括半导体衬底，该半导体衬底包括掩埋有第一绝缘膜的SOI区域和非SOI区域，该半导体衬底设置有形成在SOI区域与非SOI区域之间的边界区域 并且具有埋置在其中的第二绝缘膜，所述第二绝缘膜从所述SOI区域侧向非SOI区域侧向上倾斜，所述第二绝缘膜的厚度小于所述第一绝缘膜的厚度， SOI区域侧，分离地形成在半导体衬底的非SOI区域中并限定元件区域的一对元件隔离绝缘区域，形成在元件区域中的一对杂质扩散区域以及栅极电极 通过半导体衬底的元件区域中的栅极绝缘膜形成。

公开(公告)号：US20050162966A1

公开(公告)日：2005-07-28

申请号：US11081581

申请日：2005-03-17

申请人： Ichiro Mizushima

发明人： Ichiro Mizushima

IPC分类号： H01L21/822 ,  G11C8/00 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10897

摘要： A semiconductor device of this invention comprises a semiconductor substrate, a plurality of memory regions provided on the semiconductor substrate, the plurality of memory regions having the same structure, and functional region provided on the semiconductor substrate, the functional region including a different function from the memory.

摘要翻译： 本发明的半导体器件包括半导体衬底，设置在半导体衬底上的多个存储区域，具有相同结构的多个存储区域和设置在半导体衬底上的功能区域，功能区域包括与 记忆。

公开(公告)号：US20050156245A1

公开(公告)日：2005-07-21

申请号：US11073617

申请日：2005-03-08

申请人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

发明人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

IPC分类号： H01L21/762 ,  H01L27/12 ,  H01L27/10

CPC分类号： H01L21/764 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

摘要翻译： 根据本发明的一个方面的半导体器件包括第一半导体层和多个第二半导体层。 第一半导体层形成在半导体衬底的第一区域中，绝缘膜和介于半导体衬底和第一半导体层之间的腔中的一个。 多个第二半导体层形成在半导体衬底的第二区域中。

公开(公告)号：US6018185A

公开(公告)日：2000-01-25

申请号：US861218

申请日：1997-05-21

申请人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Iwao Kunishima ,  Masahiro Kashiwagi

发明人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Iwao Kunishima ,  Masahiro Kashiwagi

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/76224 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002

摘要： The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

摘要翻译： 半导体器件包括具有元件区域的半导体衬底，形成在半导体衬底上以围绕元件区域的元件隔离膜，与元件区域交叉并在半导体衬底上延伸的栅极部分，栅极部分包括至少一个 形成在半导体基板上的栅极绝缘膜和形成在栅极绝缘膜上的栅极电极以及形成在栅极部分两侧的元件区域的表面上的源极/漏极区域，其中元件隔离膜的上表面是 形成在与栅极部分的上表面大致相同的平面中。

公开(公告)号：US08742592B2

公开(公告)日：2014-06-03

申请号：US13424791

申请日：2012-03-20

申请人： Satoshi Wakatsuki ,  Ichiro Mizushima ,  Atsuko Sakata ,  Masayuki Kitamura

发明人： Satoshi Wakatsuki ,  Ichiro Mizushima ,  Atsuko Sakata ,  Masayuki Kitamura

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes: forming a silicon oxide film on a semiconductor substrate; forming a via in the silicon oxide film; forming a contact layer inside the via; forming a silicon layer on the contact layer; and forming a tungsten film embedded in the via by making a tungsten-containing gas react with the silicon layer.

摘要翻译： 根据一个实施例，一种制造半导体器件的方法包括：在半导体衬底上形成氧化硅膜; 在氧化硅膜中形成通孔; 在通孔内形成接触层; 在所述接触层上形成硅层; 以及通过使含钨气体与硅层反应形成嵌入通孔中的钨膜。

公开(公告)号：US08648464B2

公开(公告)日：2014-02-11

申请号：US13413854

申请日：2012-03-07

申请人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

发明人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

IPC分类号： H01L23/48

CPC分类号： H01L21/02639 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/02645 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，公开了一种半导体器件。 该器件包括半导体衬底和半导体衬底上方的互连。 互连包括助催化剂层，助催化剂层上的催化剂层和催化剂层上的石墨烯层。 助催化剂层包括与催化剂层接触的部分。 该部分具有面平面立方结构，其中（111）面平行于半导体衬底的表面定向。 催化剂层具有面平面立方结构，其中（111）面平行于半导体衬底的表面取向。

公开(公告)号：US08551871B2

公开(公告)日：2013-10-08

申请号：US13240662

申请日：2011-09-22

申请人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

发明人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由 的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中， 从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。