公开(公告)号：US6018185A

公开(公告)日：2000-01-25

申请号：US861218

申请日：1997-05-21

申请人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Iwao Kunishima ,  Masahiro Kashiwagi

发明人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Iwao Kunishima ,  Masahiro Kashiwagi

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/76224 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002

摘要： The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

摘要翻译： 半导体器件包括具有元件区域的半导体衬底，形成在半导体衬底上以围绕元件区域的元件隔离膜，与元件区域交叉并在半导体衬底上延伸的栅极部分，栅极部分包括至少一个 形成在半导体基板上的栅极绝缘膜和形成在栅极绝缘膜上的栅极电极以及形成在栅极部分两侧的元件区域的表面上的源极/漏极区域，其中元件隔离膜的上表面是 形成在与栅极部分的上表面大致相同的平面中。

公开(公告)号：US06342421B1

公开(公告)日：2002-01-29

申请号：US09098736

申请日：1998-06-18

申请人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

发明人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

IPC分类号： H01L27108

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/456 ,  H01L29/458 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78618

摘要： A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在具有用于形成硅区域的暴露区域的开口的绝缘膜的表面上具有硅区域的衬底的硅区上形成绝缘膜的步骤，提供含有 卤素到硅区域，并且将硅源气体供应到硅区域上，由此在硅区域的暴露区域上选择性地沉积硅。

公开(公告)号：US5864161A

公开(公告)日：1999-01-26

申请号：US526696

申请日：1995-09-11

申请人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

发明人： Yuichiro Mitani ,  Ichiro Mizushima ,  Shigeru Kambayashi ,  Hirotaka Nishino ,  Masahiro Kashiwagi

IPC分类号： H01L21/302 ,  H01L21/20 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76

CPC分类号： H01L29/78618 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/456 ,  H01L29/458 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在具有用于形成硅区域的暴露区域的开口的绝缘膜的表面上的具有硅区域的衬底的硅区上形成绝缘膜的步骤，提供含有 卤素到硅区域，并且将硅源气体供应到硅区域上，由此在硅区域的暴露区域上选择性地沉积硅。

公开(公告)号：US06395621B1

公开(公告)日：2002-05-28

申请号：US09998642

申请日：2001-12-03

申请人： Ichiro Mizushima ,  Yuichiro Mitani ,  Shigeru Kambayashi ,  Kiyotaka Miyano

发明人： Ichiro Mizushima ,  Yuichiro Mitani ,  Shigeru Kambayashi ,  Kiyotaka Miyano

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2022 ,  H01L29/665 ,  H01L29/66628

摘要： A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth. Thus, a silicon epitaxial single crystal layer exhibiting high quality is formed on the silicon substrate. The present invention is suitable as a process for manufacturing a high-speed and high degree of integration of a semiconductor device having an elevated source/drain structure and a SALICIDE structure.

摘要翻译： 提供了在半导体衬底上沉积非晶硅或多晶硅的工艺。 然后，采用低温固相生长方法，仅在半导体衬底的暴露部分上选择性地形成非晶硅或多晶硅为单晶硅。 用于制造具有高制造成本，低成本和高质量的外延硅衬底的步骤可用于制造包含收缩MOS晶体管的半导体器件的工艺。 具体地说，在硅衬底上形成厚度不大于单分子层的氧化硅层。 然后，在低温区域的氧化硅层上沉积非晶硅层，以在低温区域进行退火。 因此，由于固相生长，非晶硅层变为单晶。 因此，在硅衬底上形成表现出高质量的硅外延单晶层。 本发明适用于制造具有升高的源/漏结构和SALICIDE结构的半导体器件的高速和高度集成的方法。

公开(公告)号：US06346732B1

公开(公告)日：2002-02-12

申请号：US09568548

申请日：2000-05-11

申请人： Ichiro Mizushima ,  Yuichiro Mitani ,  Shigeru Kambayashi ,  Kiyotaka Miyano

发明人： Ichiro Mizushima ,  Yuichiro Mitani ,  Shigeru Kambayashi ,  Kiyotaka Miyano

IPC分类号： H01L2976

CPC分类号： H01L21/02667 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2022 ,  H01L29/665 ,  H01L29/66628

摘要： A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth. Thus, a silicon epitaxial single crystal layer exhibiting high quality is formed on the silicon substrate. The present invention is suitable as a process for manufacturing a high-speed and high degree of integration of a semiconductor device having an elevated source/drain structure and a SALICIDE structure.

摘要翻译： 提供了在半导体衬底上沉积非晶硅或多晶硅的工艺。 然后，采用低温固相生长方法，仅在半导体衬底的暴露部分上选择性地形成非晶硅或多晶硅为单晶硅。 用于制造具有高制造成品率，低成本和高质量的外延硅衬底的步骤可用于制造包含收缩MOS晶体管的半导体器件的工艺。 具体地说，在硅衬底上形成厚度不大于单分子层的氧化硅层。 然后，在低温区域的氧化硅层上沉积非晶硅层，以在低温区域进行退火。 因此，由于固相生长，非晶硅层变为单晶。 因此，在硅衬底上形成表现出高质量的硅外延单晶层。 本发明适用于制造具有升高的源/漏结构和SALICIDE结构的半导体器件的高速和高度集成的方法。

公开(公告)号：US5879447A

公开(公告)日：1999-03-09

申请号：US478765

申请日：1995-06-07

申请人： Takako Okada ,  Shigeru Kambayashi ,  Moto Yabuki ,  Shinji Onga ,  Yoshitaka Tsunashima ,  Yuuichi Mikata ,  Haruo Okano

发明人： Takako Okada ,  Shigeru Kambayashi ,  Moto Yabuki ,  Shinji Onga ,  Yoshitaka Tsunashima ,  Yuuichi Mikata ,  Haruo Okano

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/329 ,  H01L21/334 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  C30B19/00

CPC分类号： H01L28/82 ,  H01L21/2022 ,  H01L21/28035 ,  H01L29/6609 ,  H01L29/66181 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/49 ,  H01L29/78654

摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

公开(公告)号：US5582640A

公开(公告)日：1996-12-10

申请号：US56443

申请日：1993-04-30

申请人： Takako Okada ,  Shigeru Kambayashi ,  Moto Yabuki ,  Shinji Onga ,  Yoshitaka Tsunashima ,  Yuuichi Mikata ,  Haruo Okano

发明人： Takako Okada ,  Shigeru Kambayashi ,  Moto Yabuki ,  Shinji Onga ,  Yoshitaka Tsunashima ,  Yuuichi Mikata ,  Haruo Okano

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/329 ,  H01L21/334 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L28/82 ,  H01L21/2022 ,  H01L21/28035 ,  H01L29/6609 ,  H01L29/66181 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/49 ,  H01L29/78654

摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

公开(公告)号：US07239278B2

公开(公告)日：2007-07-03

申请号：US10885080

申请日：2004-07-07

申请人： Takashi Koiso ,  Kanako Hattori ,  Naoki Imasaki ,  Shigeru Kambayashi

发明人： Takashi Koiso ,  Kanako Hattori ,  Naoki Imasaki ,  Shigeru Kambayashi

IPC分类号： G01S3/02

CPC分类号： G01S5/0252 ,  G01S5/14

摘要： A detection system includes a sensitiveness level setup control section and a receiver control section. The sensitiveness level setup control section looks into a sensitiveness level setup file and finds the sequence of levels of sensitiveness to the received signals corresponding to the setup ID. The receiver control section converts, for each component, a sequence of levels of sensitiveness to received signals received from the sensitiveness level switching section into signals for designating levels of sensitiveness to received signals corresponding to the respective receivers, and transmits the signals for designating levels of sensitiveness to received signals through the communication network.

摘要翻译： 检测系统包括敏感度设置控制部分和接收器控制部分。 敏感度设置控制部分查看敏感度设置文件，并且找到对应于设置ID的接收信号的敏感度级别的顺序。 接收机控制部分针对每个分量将从敏感度电平切换部分接收到的接收信号的敏感度级序列转换成用于指定对与各个接收机相对应的接收信号的敏感度的信号，并且发送用于指定等级的信号 通过通信网络对接收到的信号敏感。

公开(公告)号：US20050046577A1

公开(公告)日：2005-03-03

申请号：US10885080

申请日：2004-07-07

申请人： Takashi Koiso ,  Kanako Hattori ,  Naoki Imasaki ,  Shigeru Kambayashi

发明人： Takashi Koiso ,  Kanako Hattori ,  Naoki Imasaki ,  Shigeru Kambayashi

IPC分类号： G08B25/00 ,  G01S5/02 ,  G01S5/14 ,  G01S13/74 ,  G08B23/00 ,  G08B25/08 ,  G08B25/10 ,  H04W4/02 ,  H04W64/00

CPC分类号： G01S5/0252 ,  G01S5/14

摘要： A detection system includes a sensitiveness level setup control section and a receiver control section. The sensitiveness level setup control section looks into a sensitiveness level setup file and finds the sequence of levels of sensitiveness to the received signals corresponding to the setup ID. The receiver control section converts, for each component, a sequence of levels of sensitiveness to received signals received from the sensitiveness level switching section into signals for designating levels of sensitiveness to received signals corresponding to the respective receivers, and transmits the signals for designating levels of sensitiveness to received signals through the communication network.

摘要翻译： 检测系统包括敏感度设置控制部分和接收器控制部分。 敏感度设置控制部分查看敏感度设置文件，并且找到对应于设置ID的接收信号的敏感度级别的顺序。 接收机控制部分针对每个分量将从敏感度电平切换部分接收到的接收信号的灵敏度级别序列转换成用于指定对与各个接收机对应的接收信号的敏感度的信号，并且发送用于指定等级的信号 通过通信网络对接收到的信号敏感。

公开(公告)号：US5981150A

公开(公告)日：1999-11-09

申请号：US888280

申请日：1997-07-03

申请人： Masami Aoki ,  Shigeru Kambayashi ,  Junichi Wada ,  Yasuhiko Sato

发明人： Masami Aoki ,  Shigeru Kambayashi ,  Junichi Wada ,  Yasuhiko Sato

IPC分类号： G03F7/20 ,  H01L21/027

CPC分类号： G03F7/2008 ,  H01L21/0274

摘要： The present invention provides a method for forming a resist pattern which allows a closest pattern to be formed thus solving a problem of misalignment. A substrate has, on the surface thereof, first and second domains having different reflectivity to first light. A resist covers the first and second domains. The first light illuminates the resist and reflects from the surfaces of the first and second domains. A resist pattern forms in the fashion of self-alignment based on the illuminated and reflected light. The sum of the exposure of the illuminated and reflected light is set above a threshold of exposure by which the resist is sensitized in the first domain and set below the threshold of exposure in the second domain.

摘要翻译： 本发明提供一种形成抗蚀剂图案的方法，其允许形成最近的图案，从而解决了未对准的问题。 基板在其表面上具有与第一光不同的反射率的第一和第二畴。 抗蚀剂覆盖第一和第二域。 第一光照亮抗蚀剂并从第一和第二畴的表面反射。 抗蚀图案基于照明和反射光以自对准的方式形成。 照射和反射光的曝光总和设定在暴露阈值以上，抗蚀剂在第一域中被致敏并设定在第二域内的曝光阈值以下。