公开(公告)号：US06251771B1

公开(公告)日：2001-06-26

申请号：US09255466

申请日：1999-02-22

申请人： Patricia B. Smith ,  Girish A. Dixit ,  Eden Zielinski ,  Stephen W. Russell

发明人： Patricia B. Smith ,  Girish A. Dixit ,  Eden Zielinski ,  Stephen W. Russell

IPC分类号： H01L214763

CPC分类号： H01L21/3212 ,  H01L21/321

摘要： An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step 102 of FIG. 1); forming a layer of the metallic conductor on the dielectric layer (step 104 of FIG. 1); removing a portion of the layer of the metallic conductor on the dielectric layer (step 106 of FIG. 1); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step 110 of FIG. 1). Preferably, the plasma contains a substance selected from the group consisting of: NH3, N2H2, H2S, and CH4, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof. The step of removing a portion of the layer of the metallic conductor is, preferably, performed by sputtering off a portion of the metallic conductor, chemical-mechanical polishing, etching, or a combination thereof.

摘要翻译： 本发明的一个实施例是一种在半导体衬底上形成电子器件并具有至少一层金属导体的方法，该方法包括以下步骤：在半导体衬底上形成电介质层，电介质层具有开口（ 图1的步骤102）; 在介电层上形成金属导体层（图1的步骤104）; 去除介电层上的金属导体层的一部分（图1的步骤106）; 并将暴露的金属导体经受含有氢或氘的等离子体，以使金属导体钝化（图1的步骤110）。 优选地，等离子体包含选自由NH 3，N 2 H 2，H 2 S和CH 4组成的组的物质，金属导体由选自铜，铜掺杂的铝，Ag，Sn，Pb ，Ti，Cr，Mg，Ta及其任意组合。 优选地，通过溅射金属导体的一部分，化学机械抛光，蚀刻或其组合来去除金属导体的该层的一部分的步骤。

公开(公告)号：US06878245B2

公开(公告)日：2005-04-12

申请号：US10085338

申请日：2002-02-27

申请人： Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Sivakami Ramanathan ,  Muhammad Atif Malik ,  Girish A. Dixit

发明人： Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Sivakami Ramanathan ,  Muhammad Atif Malik ,  Girish A. Dixit

IPC分类号： C25D21/14 ,  C25D21/18 ,  C25D17/00 ,  C25D21/00

CPC分类号： C25D21/18 ,  C25D21/14

摘要： Embodiments of the invention generally provide an apparatus and method for replenishing organic molecules in an electroplating bath. The replenishment process of the present invention may occur on a real-time basis, and therefore, the concentration of organics minimally varies from desired concentration levels. The replenishment method generally includes conducting pre-processing depletion measurements in order to determine organic depletion rates per current density applied in the electroplating system. Once the organic depletion rates per current density are determined, these depletion rates may be applied to an electroplating processing recipe to calculate the volume of organic depletion per recipe step. The calculated volume of organic depletion per recipe step may then be used to determine the volume of organic molecule replenishment per unit of time that is required per recipe step in order to maintain a desired concentration of organics in the plating solution. The calculated replenishment volume may then be added to the processing recipe so that the replenishment process may occur at real-time during processing periods. The apparatus generally includes a selectively actuated valve in communicaiton with a fluid delivery line, wherein the valve is configured to fluidly isolate a plating cell during a non-processing time period. The valve may be controlled by a system controller, and thus, the fluid level in the cell may be controlled during a non-processing time period.

摘要翻译： 本发明的实施方案通常提供用于在电镀浴中补充有机分子的装置和方法。 本发明的补充方法可以在实时的基础上进行，因此有机物的浓度最小化从期望的浓度水平变化。 补充方法通常包括进行预处理耗尽测量，以便确定在电镀系统中施加的每个电流密度的有机耗尽率。 一旦确定了每个电流密度的有机耗尽率，则这些耗尽率可以应用于电镀处理配方以计算每个配方步骤的有机耗尽量。 然后可以使用每个配方步骤的计算的有机耗尽体积来确定每个配方步骤所需的每单位时间的有机分子补充体积，以维持电镀溶液中所需的有机物浓度。 计算的补充量然后可以被添加到处理配方中，使得补货过程可以在处理时段期间实时发生。 该装置通常包括与流体输送管线通信的选择性致动的阀，其中阀被配置为在非处理时间段期间流体地隔离电镀槽。 阀可以由系统控制器控制，因此，可以在非处理时间段期间控制单元中的液位。

公开(公告)号：US06358849B1

公开(公告)日：2002-03-19

申请号：US09467680

申请日：1999-12-21

申请人： Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

发明人： Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

IPC分类号： H01L21302

CPC分类号： H01L21/76808 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867

摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

摘要翻译： 一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。 这在沟槽蚀刻期间通过底部保护提供。

公开(公告)号：US06333265B1

公开(公告)日：2001-12-25

申请号：US08766199

申请日：1996-12-12

申请人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

发明人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

IPC分类号： H01L2144

CPC分类号： H01L21/76882 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76862

摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

摘要翻译： 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地 在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。

公开(公告)号：US06268297B1

公开(公告)日：2001-07-31

申请号：US09196725

申请日：1998-11-20

申请人： Somnath S. Nag ,  Gregory B. Shinn ,  Girish A. Dixit

发明人： Somnath S. Nag ,  Gregory B. Shinn ,  Girish A. Dixit

IPC分类号： H01L21469

CPC分类号： H01L21/02304 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31604 ,  H01L21/31625 ,  H01L21/76801

摘要： A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.

摘要翻译： 在高密度等离子体化学气相沉积技术中使用基于膦的化学的低温预金属介电沉积方法。 该方法使用在低于350℃下沉积的高达3.5％（重量）的磷掺杂氧化物，能够在没有微孔的多晶硅栅极之间填充0.4微米的空间。

公开(公告)号：US06159847A

公开(公告)日：2000-12-12

申请号：US191027

申请日：1998-11-12

申请人： Robert H. Havemann ,  Girish A. Dixit

发明人： Robert H. Havemann ,  Girish A. Dixit

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/7685 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： AlCu alloys with higher Cu content are added in thin layers within a metallization structure. The increased Cu content provided by the thin layer improves interconnect reliability and reduces the effects of electromigration with minimal effect on plasma etch and cleanup processes.

摘要翻译： 具有较高Cu含量的AlCu合金以金属化结构内的薄层加入。 由薄层提供的增加的Cu含量提高了互连可靠性，并且减少电迁移的影响，对等离子体蚀刻和清除过程的影响最小。

公开(公告)号：US5849367A

公开(公告)日：1998-12-15

申请号：US764674

申请日：1996-12-11

申请人： Girish A. Dixit ,  Anthony J. Konecni

发明人： Girish A. Dixit ,  Anthony J. Konecni

IPC分类号： C23C14/02 ,  H01L21/768

CPC分类号： H01L21/76846 ,  C23C14/022 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877

摘要： An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.

摘要翻译： 提供了元素无钛衬里和空腔清洁工艺，其允许消除常规的溅射蚀刻和元素钛沉积。 低功率等离子体蚀刻提供诸如触点和通孔之类的空腔的预调节/清洁。 提供难熔金属作为空腔衬垫。 优选地，衬套由几个分立的难熔金属衬垫层组成，每层具有约25-100的厚度，可以通过CVD和/或PVD施加。 优选地，在每个衬垫层沉积之间插入低功率等离子体清洁。 可以将合适的金属塞子沉积并引导到空腔中以完成空腔填充。 优选地，金属插塞是元素铝或铝合金插塞，其通过CVD沉积并强力填充到空腔中以减少空腔内的微孔的入射。 消除常规的溅射蚀刻和与这种处理相关的高温处理（温度> = = DIFFERENCE 400℃）允许使用聚合物电介质，例如聚四氟乙烯（“PTFE”）族化合物，其表现出 介电常数（kappa）约为1.9; 聚对二甲苯（kappa = DIFFERENCE 2.2-2.6）; 气凝胶和干凝胶（kappa = DIFFERENCE 1.1-1.8）; 和聚合物旋涂玻璃（“SOG”）材料的家族; 使用所有上述材料是有吸引力的，因为这些材料能够减少互连的寄生电容。 由于这些聚合物材料是温度敏感的，因此其使用受到限制，因为传统的器件制造实践通常需要远远超过这些材料的熔化和/或分解温度的操作温度。

公开(公告)号：US5278098A

公开(公告)日：1994-01-11

申请号：US939951

申请日：1992-09-03

申请人： Che C. Wei ,  Chiara Zaccherini ,  Robert O. Miller ,  Girish A. Dixit

发明人： Che C. Wei ,  Chiara Zaccherini ,  Robert O. Miller ,  Girish A. Dixit

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/88 ,  H01L21/316 ,  H01L21/78

CPC分类号： H01L21/76889 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53271 ,  H01L2924/0002

摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

摘要翻译： 沉积并图案化多晶硅层以限定互连水平。 然后对下导电层的接触开口进行限定和图案化。 诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。 这提供了低电阻互连，以及良好的金属触点到底层。 使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

公开(公告)号：US07115534B2

公开(公告)日：2006-10-03

申请号：US10847891

申请日：2004-05-18

申请人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

发明人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76808

摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

摘要翻译： 提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。 在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。 通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

公开(公告)号：US06821909B2

公开(公告)日：2004-11-23

申请号：US10284855

申请日：2002-10-30

申请人： Sivakami Ramanathan ,  Deenesh Padhi ,  Srinivas Gandikota ,  Girish A. Dixit

发明人： Sivakami Ramanathan ,  Deenesh Padhi ,  Srinivas Gandikota ,  Girish A. Dixit

IPC分类号： H01L2131

CPC分类号： H01L21/76877 ,  C23C18/166 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/1879 ,  C23C18/1882 ,  C23C18/34 ,  C23C18/36 ,  C23C18/44 ,  C23C18/50 ,  C23G1/10 ,  H01L21/288 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76883

摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.

摘要翻译： 提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。 该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用 酸性溶液。 在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。 在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。 在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。