公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US10290712B1

公开(公告)日：2019-05-14

申请号：US15797606

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

公开(公告)号：US10211206B1

公开(公告)日：2019-02-19

申请号：US15800905

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: Methods of connecting a read driver transistor to a PD and PU inverter of a two-port vertical SRAM via a shared GAA or a vertical cross-couple contact between a GAA of the read driver transistor and the bottom source/drain region of the PD and PU inverter and the resulting devices are provided. Embodiments include forming a first PD transistor, a first PU transistor, a second PU transistor, and a second PD transistor over a substrate; forming a first PG transistor and a second PG transistor over the substrate; forming a read transistor and a read driver transistor laterally separated in the first direction over the substrate, the read transistor and the read driver transistor adjacent to the second PG transistor and the first PD transistor, respectively; and connecting the read driver transistor, the first PD transistor, and the first PU transistor.

公开(公告)号：US20190035791A1

公开(公告)日：2019-01-31

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/10814 ,  B82Y10/00 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/1248 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US10164006B1

公开(公告)日：2018-12-25

申请号：US15797701

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.

公开(公告)号：US09876010B1

公开(公告)日：2018-01-23

申请号：US15342464

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L23/62 ,  H01L27/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L23/5228 ,  H01L29/4232 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A resistor is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. The resistor is composed of a material suitable to provide a predetermined resistance to a current to be conducted therethrough. A pair of resistor contacts are electrically connected to the resistor and spaced to provide the predetermined resistance to the current.

公开(公告)号：US09666709B2

公开(公告)日：2017-05-30

申请号：US14609105

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoli He ,  Yanxiang Liu ,  Jerome Ciavatti ,  Myung Hee Nam

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L29/7816 ,  H01L21/0332 ,  H01L21/32 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7835

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

公开(公告)号：US20160056265A1

公开(公告)日：2016-02-25

申请号：US14922308

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.

Abstract translation: 在半导体衬底中形成隔离区域以横向限定并电隔离器件区域，并且在器件区域中形成第一和第二横向相邻阱区域。 在器件区域上方形成栅极结构，使得第一阱区域延伸到整个栅极结构的下方，并且形成在第一阱区域和第二阱区域之间的阱区域界面从栅极结构的漏极侧边缘横向偏移。 源极和漏极区域形成在器件区域中，使得源极区域从栅极结构的源极侧边缘横向延伸并跨越第一阱区域的第一部分延伸到隔离区域的第一内部边缘，并且漏极区域 从排水侧边缘横向延伸并穿过第一井区域的第二部分。

公开(公告)号：US09178053B2

公开(公告)日：2015-11-03

申请号：US14579122

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract translation: 本文公开的一个示例性器件包括位于栅极结构的相对侧上的有源区域中的多个源极/漏极区域，每个源极/漏极区域在晶体管的栅极长度方向上具有横向宽度，并且多个卤素 区域，其中每个光晕区域位于多个源极/漏极区域中的一个的横向宽度的一部分但不是全部的下方。 本文公开的方法包括在有源区域中形成多个晕轮注入区域，其中每个晕轮植入区域的外边缘与隔离区域的相邻内边缘横向间隔开。

公开(公告)号：US08962441B2

公开(公告)日：2015-02-24

申请号：US13927932

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L21/76 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/70 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.