公开(公告)号：US20190013397A1

公开(公告)日：2019-01-10

申请号：US15642732

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02

Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.

公开(公告)号：US10115719B2

公开(公告)日：2018-10-30

申请号：US14928272

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jagar Singh ,  Sanford Chu

IPC: H01L23/552 ,  H01L27/06 ,  H01L49/02

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

公开(公告)号：US20180108732A1

公开(公告)日：2018-04-19

申请号：US15292808

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haifeng Sheng ,  Jinping Liu ,  Shesh Mani Pandey ,  Jagar Singh

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/0661 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.

公开(公告)号：US09780212B2

公开(公告)日：2017-10-03

申请号：US14030458

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc

Inventor： Jagar Singh

IPC: H01L29/78 ,  H01L21/66 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L22/14 ,  H01L29/66795

Abstract: A method for accurately electrically measuring a width of a fin of a FinFET, using a semiconductor fin quantum well structure is provided. The semiconductor fin quantum well structure includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fin is sandwiched by an electrical isolation layer from a top and a first side and a second side across from the first side, to create a semiconductor fin quantum well. At least one gate material is provided on each side of the electrical isolation layer. A dielectric layer is provided over the top of the electrical isolation layer to further increase the electrical isolation between the gate materials. The width of the semiconductor fin is measured accurately by applying a resonant bias voltage across the fin by applying voltage on the gate materials from either side. The peak tunneling current generated by the applied resonant bias voltage is used to measure width of the fin.

公开(公告)号：US09704966B1

公开(公告)日：2017-07-11

申请号：US15218318

申请日：2016-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/861 ,  H01L27/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.

公开(公告)号：US20170162647A1

公开(公告)日：2017-06-08

申请号：US15437057

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L49/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/06 ,  H01L27/07

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L27/0629 ,  H01L27/0738 ,  H01L27/0802 ,  H01L27/101 ,  H01L29/7831 ,  H01L29/785

Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.

公开(公告)号：US09647145B1

公开(公告)日：2017-05-09

申请号：US15012563

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Josef Watts

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L27/0814 ,  H01L27/0629 ,  H01L29/0657 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/8611

Abstract: Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin.

公开(公告)号：US09620587B2

公开(公告)日：2017-04-11

申请号：US14871181

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45 ,  H01L29/861 ,  H01L29/866

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US09601486B2

公开(公告)日：2017-03-21

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US09601428B2

公开(公告)日：2017-03-21

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC: H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/06 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.