公开(公告)号：US20160126245A1

公开(公告)日：2016-05-05

申请号：US14527278

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L27/1087 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10879

Abstract: Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

Abstract translation: 公开了用替代金属栅极技术形成eDRAM的方法和所得到的器件。 实施例包括在基板上形成第一和第二虚设电极，每个虚设电极在相对侧具有隔离物并被ILD包围; 去除第一和第二虚拟电极，分别形成第一和第二腔; 在所述基板上形成硬掩模，暴露所述第一腔体; 通过第一腔形成衬底中的深沟槽; 移除硬掩模; 以及在所述第一腔和深沟槽中形成电容器，并且在所述第二腔中同时形成存取晶体管。

公开(公告)号：US20160118500A1

公开(公告)日：2016-04-28

申请号：US14523548

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

公开(公告)号：US20150332972A1

公开(公告)日：2015-11-19

申请号：US14279480

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jianwei PENG ,  Min-hwa CHI

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

Abstract translation: 提供了一种制造包括凸起接触结构的凸起鳍结构的方法。 该方法可以包括：提供底鳍结构; 提供至少一个辅助翅片结构，所述至少一个辅助翅片结构在所述基部翅片结构的一侧与所述底部翅片结构接触; 在基板结构上生长材料以形成凸起的翅片结构; 并且在所述至少一个辅助翅片结构上生长所述材料，其中所述至少一个辅助翅片结构接触所述基底翅片结构增加了在所述基底翅片结构与所述至少 一个辅助翅片结构形成凸起的接触结构。

公开(公告)号：US20190326436A1

公开(公告)日：2019-10-24

申请号：US16433626

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/161 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US20180069092A1

公开(公告)日：2018-03-08

申请号：US15258333

申请日：2016-09-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20170288016A1

公开(公告)日：2017-10-05

申请号：US15627973

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing WONG ,  Min-hwa CHI ,  Tae-Hoon KIM

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

公开(公告)号：US20170207090A1

公开(公告)日：2017-07-20

申请号：US15000111

申请日：2016-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin PENG ,  Min-hwa CHI

IPC: H01L21/225 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US20170125361A1

公开(公告)日：2017-05-04

申请号：US14926880

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Min-hwa CHI ,  Ajey Poovannummoottil JACOB

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5252

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

公开(公告)号：US20170069759A1

公开(公告)日：2017-03-09

申请号：US14847462

申请日：2015-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7853 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/66818

Abstract: A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping, after removal of the dummy gate and before a replacement metal gate is formed.

Abstract translation: 三维晶体管包括在去除伪栅极之后并且在替换金属栅极形成之前具有去除中心部分（叉形沟道）或侧部（窄沟道）或不形成的鳍的沟道。

公开(公告)号：US20160284846A1

公开(公告)日：2016-09-29

申请号：US14667872

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/04 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7391 ,  H01L29/7847

Abstract: Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a tunneling field-effect transistor comprising a substrate; a source and a drain within the substrate; a gate between the source and the drain; and a stacking fault within the source.

Abstract translation: 公开了包括源的堆垛故障或者TFET的源极和漏极的装置，以改善隧道效率。 实施例可以包括隧道场效应晶体管，其包括衬底; 衬底内的源极和漏极; 源极和漏极之间的栅极; 和源内的堆垛故障。