公开(公告)号：US20090057906A1

公开(公告)日：2009-03-05

申请号：US11896034

申请日：2007-08-29

申请人： Steven Mark Buchoff ,  Andrew Christian Loyd ,  Robert S. Howell

发明人： Steven Mark Buchoff ,  Andrew Christian Loyd ,  Robert S. Howell

IPC分类号： H01L23/48 ,  H01L21/477

CPC分类号： H01L21/0485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a silicide contact. The method comprises the steps of depositing a metal on a SiC substrate; forming an encapsulating layer on deposited metal; and annealing said deposited metal to form a suicide contact. The encapsulating layer prevents agglomeration and formation of stringers during the annealing process.

摘要翻译： 一种硅化物接触的制造方法。 该方法包括以下步骤：在SiC衬底上沉积金属; 在沉积的金属上形成封装层; 并退火所述沉积的金属以形成硅化物接触。 封装层在退火过程中防止了桁条的聚集和形成。

公开(公告)号：US10985243B2

公开(公告)日：2021-04-20

申请号：US16992244

申请日：2020-08-13

申请人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

发明人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L23/29 ,  H01L23/31 ,  H01L29/15 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/778 ,  H01L29/66

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

公开(公告)号：US10784341B2

公开(公告)日：2020-09-22

申请号：US16252952

申请日：2019-01-21

申请人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

发明人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L23/29 ,  H01L23/31 ,  H01L29/15 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/778 ,  H01L29/66

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

公开(公告)号：US10069093B2

公开(公告)日：2018-09-04

申请号：US15642066

申请日：2017-07-05

申请人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

发明人： James T. Kelliher ,  Monica P. Lilly ,  Robert S. Howell ,  Wayne Stephen Miller ,  Patrick B. Shea ,  Matthew J. Walker ,  William J. Sweet

IPC分类号： H01L51/00 ,  H01L29/76 ,  H01L51/05

摘要： One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

公开(公告)号：US09385224B2

公开(公告)日：2016-07-05

申请号：US14458906

申请日：2014-08-13

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/76 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/66

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

摘要翻译： 公开了一种集成电路，其包括具有在单通道器件区域中覆盖衬底结构的单个共享异质结构的第一部分的单通道器件，以及与单个共用异质结构的第一部分接触的栅极接触。 集成电路还包括多通道器件，其包括覆盖多通道器件区域中的衬底结构的单个共享异质结构的第二部分，覆盖在单个共用异质结构的第二部分上的阻挡层，以及覆盖在阻挡层上的超晶格结构， 超晶格结构包括多个异质结构。 单个共享异质结构中的隔离区域将单通道器件与多通道器件隔离。

公开(公告)号：US20090194870A1

公开(公告)日：2009-08-06

申请号：US12023831

申请日：2008-01-31

申请人： Harvey C. Nathanson ,  Robert M. Young ,  Joseph T. Smith ,  Robert S. Howell ,  Archer S. Mitchell

发明人： Harvey C. Nathanson ,  Robert M. Young ,  Joseph T. Smith ,  Robert S. Howell ,  Archer S. Mitchell

IPC分类号： H01L23/34 ,  H01L35/00

CPC分类号： H01L35/00 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates to a Point Cooler based on a combination of principles, including large area, low current density PN junction cooling, and electron emission from heavily doped shallowly-depleted P tips. Using Junction Cooling rather than thermoelectric cooling enables an all silicon device to be made that favorably competes with the commercial thermoelectric cooling systems. Theoretical values of THOT/TCOLD of 6 or more (in contrast to about 1.5 for other solid state refrigerators) predict this single-stage solid state vacuum electronic cooler can approach 50K at light loading, significantly lower than conventional Bismuth Telluride based thermo electrics. The high Z values for PN junction cooling with wire connection and Tunnel heat extraction opens up solid state vibration-less form fit and function replacement cooling.

摘要翻译： 本公开涉及基于原理组合的点冷却器，包括大面积，低电流密度PN结冷却和来自重掺杂的浅耗尽P尖端的电子发射。 使用接合冷却而不是热电冷却使得所有的硅器件能够被制造成与商业热电冷却系统相竞争。 THOT / TCOLD的理论值为6以上（与其他固态冰箱的1.5倍相比）预测，这种单级固态真空电子式冷却器在轻载时可达到50K，明显低于传统的碲化铋基热电。 通过电线连接和隧道热提取的PN结冷却的高Z值打开固态无振动形式配合和功能更换冷却。

公开(公告)号：US07560322B2

公开(公告)日：2009-07-14

申请号：US11248195

申请日：2005-10-13

申请人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

发明人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

IPC分类号： H01L21/338 ,  H01L21/30

CPC分类号： H01L21/76256 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/735 ,  H01L29/7787

摘要： A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

摘要翻译： 用于大功率半导体器件的衬底布置包括在SiC晶片的表面上沉积有Si层的SiC晶片。 具有Si的第一层，SiO 2的中间层和Si的第三层的SOI结构具有与沉积在SiC晶片上的Si结合的第三层Si，形成整体结构。 除去SOI的第一层和SiO 2的中间层，留下可以制造各种半导体器件的纯的第三层Si。 可以在衬底布置的一部分上去除第三层Si和沉积的Si层，使得可以在SiC晶片上制造一个或多个半导体器件，而其他半导体器件可以容纳在纯的第三层Si上。