利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

39 条记录 (耗时 0.058 秒)

    Bus interface timing adjustment device, method and application chip
    31.
    发明授权
    Bus interface timing adjustment device, method and application chip 有权
    总线接口定时调整装置，方法和应用芯片

    公开(公告)号：US06877103B2

    公开(公告)日：2005-04-05

    申请号：US10055567

    申请日：2002-01-22

    申请人： Hung-Yi Kuo ,  I-Ming Lin

    发明人： Hung-Yi Kuo ,  I-Ming Lin

    IPC分类号： G11C7/22 ,  G11C29/02 ,  G06F1/04 ,  G06F1/14

    CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/50012

    摘要： A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

    摘要翻译： 总线接口的定时调整装置，方法和芯片。 通过重复调整时钟信号到总线接口的相移量，对总线接口进行读/写测试，检查读/写数据的正确性，将存储器总线时钟信号中的相移适用于 确定正常运行。 因此，发现总线接口定时信号中的相移量的安全范围，并且总线接口定时信号的相移被设置为安全范围的中点。 该方法还可以应用于系统总线以及控制芯片组总线和存储器总线之间的信号的定时调整。

    Wafer level photonic device die structure and method of making the same
    32.
    发明授权
    Wafer level photonic device die structure and method of making the same 有权
    晶圆级光子器件芯片结构及其制作方法

    公开(公告)号：US08604491B2

    公开(公告)日：2013-12-10

    申请号：US13188020

    申请日：2011-07-21

    申请人： Chih-Kuang Yu ,  Hung-Yi Kuo

    发明人： Chih-Kuang Yu ,  Hung-Yi Kuo

    IPC分类号： H01L33/60

    CPC分类号： H01L33/62 ,  H01L33/005 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/08 ,  H01L33/22 ,  H01L33/32 ,  H01L33/382 ,  H01L33/405 ,  H01L33/486 ,  H01L33/502 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A vertical Light Emitting Diode (LED) device includes an epi structure with a first-type-doped portion, a second-type-doped portion, and a quantum well structure between the first-type-doped and second-type-doped portions and a carrier structure with a plurality of conductive contact pads in electrical contact with the epi structure and a plurality of bonding pads on a side of the carrier structure distal the epi structure, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL). The vertical LED device further includes a first insulating film on a side of the carrier structure proximal the epi structure and a second insulating film on a side of the carrier structure distal the epi structure.

    摘要翻译： 垂直发光二极管（LED）装置包括在第一掺杂掺杂部分和第二掺杂部分之间具有第一掺杂部分，第二掺杂部分和量子阱结构的外延结构，以及 具有与外延结构电接触的多个导电接触焊盘和在外延结构远侧的载体结构侧的多个接合焊盘的载体结构，其中导电接触焊盘与接合焊盘使用 至少一个通孔和再分发层（RDL）。 垂直LED器件还包括在靠近外延结构的载体结构侧的第一绝缘膜和远离外延结构的载体结构侧的第二绝缘膜。

    CHIPSETS AND CLOCK GENERATION METHODS THEREOF
    39.
    发明申请
    CHIPSETS AND CLOCK GENERATION METHODS THEREOF 有权
    CHIPSETS及其产生方法

    公开(公告)号：US20090121758A1

    公开(公告)日：2009-05-14

    申请号：US12102119

    申请日：2008-04-14

    申请人： Chia-Hung Su ,  Hung-Yi Kuo

    发明人： Chia-Hung Su ,  Hung-Yi Kuo

    IPC分类号： H03L7/06

    CPC分类号： H03L7/14 ,  H03L7/18

    摘要： Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock.

    摘要翻译： 提供能够防止由反馈时钟失真引起的故障的芯片组，其中相位频率检测器根据第一参考时钟和第一反馈时钟产生控制电压，压控振荡器根据控制电压产生输出时钟， 分频器对第二反馈时钟进行分频以获得第一反馈时钟，频率滤波器从外部单元估计第三反馈时钟的摆动和频率，并选择性地输出第三反馈时钟或输出时钟之一 作为第二个时钟。