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166 条记录 (耗时 0.043 秒)

    Low voltage, low power bandgap circuit
    32.
    发明授权
    Low voltage, low power bandgap circuit 有权
    低电压，低功耗带隙电路

    公开(公告)号：US09092044B2

    公开(公告)日：2015-07-28

    申请号：US13286843

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G05F3/02 ,  G05F3/30

    CPC分类号： G05F3/30

    摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.

    摘要翻译： 用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。 电流镜电路具有至少两个平行电流路径。 每个电流路径由运算放大器的输出控制。 电流路径之一耦合到运算放大器的两个输入之一。 电阻分压电路连接到另一个电流通路。 电阻分压电路提供电路的带隙电压。

    Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming
    33.
    发明申请
    Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming 有权
    非易失性存储器阵列及使用相同的分数字编程方法

    公开(公告)号：US20140104965A1

    公开(公告)日：2014-04-17

    申请号：US13652447

    申请日：2012-10-15

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

    摘要： A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

    摘要翻译： 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

    Charge pump systems and methods
    34.
    发明授权
    Charge pump systems and methods 有权
    电荷泵系统和方法

    公开(公告)号：US08232833B2

    公开(公告)日：2012-07-31

    申请号：US11805765

    申请日：2007-05-23

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    IPC分类号： G05F3/24 ,  H02M3/18

    CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

    摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

    摘要翻译： 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

    Sense amplifier for low voltage high speed sensing
    35.
    发明授权
    Sense amplifier for low voltage high speed sensing 有权
    用于低电压高速感应的感应放大器

    公开(公告)号：US08049535B2

    公开(公告)日：2011-11-01

    申请号：US12972974

    申请日：2010-12-20

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    IPC分类号： G01R19/00

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

    摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

    摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。