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    Semiconductor memory device
    36.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5345420A

    公开(公告)日：1994-09-06

    申请号：US67318

    申请日：1993-05-25

    Applicant: Hirofumi Yasuda ,  Akira Uematsu

    Inventor： Hirofumi Yasuda ,  Akira Uematsu

    IPC: G11C7/06 ,  G11C7/18 ,  G11C17/12 ,  H01L27/112 ,  G11C7/00

    CPC classification number: G11C17/12 ,  G11C7/062 ,  G11C7/18 ,  H01L27/112

    Abstract: A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit line. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.

    Abstract translation: 一种用于从所选择的存储单元读取数据的半导体存储器件。 存储单元被排列成阵列。 耦合到存储器单元的第一位线和字线被布置成矩阵。 字线选择所选单元格。 放大电路放大通过所选择的存储单元的电流并耦合到第一位线。 第二位线耦合到放大电路并且承载放大的电流。 耦合到第二位线的感测电路感测第二位线上的电流。 结果，检测到通过所选存储单元的电流。

    Sense amplifier for semiconductor memory device
    37.
    发明授权
    Sense amplifier for semiconductor memory device 失效
    用于半导体存储器件的检测放大器

    公开(公告)号：US5260899A

    公开(公告)日：1993-11-09

    申请号：US767965

    申请日：1991-09-30

    Applicant: Hirofumi Yasuda ,  Akira Uematsu

    Inventor： Hirofumi Yasuda ,  Akira Uematsu

    IPC: G11C7/06 ,  G11C7/18 ,  G11C7/00 ,  G11C11/407

    CPC classification number: G11C7/18 ,  G11C7/062

    Abstract: A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.

    Abstract translation: 一种用于从所选择的存储单元读取数据的半导体存储器件。 存储单元被排列成阵列。 耦合到存储器单元的第一位线和字线被布置成矩阵。 字线选择所选单元格。 放大电路放大通过所选择的存储单元的电流并耦合到第一位。 第二位线耦合到放大电路并且承载放大的电流。 耦合到第二位线的感测电路感测第二位线上的电流。 结果，检测到通过所选存储单元的电流。

    Semiconductor memory device
    38.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5101380A

    公开(公告)日：1992-03-31

    申请号：US527798

    申请日：1990-05-23

    Applicant: Hirofumi Yasuda ,  Toshihiko Kondo ,  Kazuo Tanaka

    Inventor： Hirofumi Yasuda ,  Toshihiko Kondo ,  Kazuo Tanaka

    IPC: G11C17/12 ,  H01L27/112

    CPC classification number: G11C17/12 ,  H01L27/112

    Abstract: A semiconductor memory device for reading stored data from a selected memory cell in the semiconductor device to a sensing amplifier. An array of memory cells is arranged in a matrix, each memory cell including a MOS transistor. Word lines are organized to select groups of the MOS transistors. A plurality of first bit lines are arrayed in a matrix with the word lines. The word lines and bit lines together select the selected memory cell from the array. Each first bit line is coupled to either the source electrode or drain electrode of a plurality of MOS transistors. There is at least one second bit line. Each second bit line is selectively coupled to at least two corresponding first bit lines. A first bit line selection circuit selectively couples one of the first bit lines to a corresponding second bit line. A first power source line is coupled to the other of the source and drain of the array of the MOS transistors. A second bit line select means selectively couples a second bit line to the sensing amplifier.

    Semiconductor memory device
    39.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4931996A

    公开(公告)日：1990-06-05

    申请号：US360611

    申请日：1989-06-02

    Applicant: Hirofumi Yasuda

    Inventor： Hirofumi Yasuda

    IPC: G11C17/12 ,  H01L27/112

    CPC classification number: G11C17/12 ,  H01L27/112

    Abstract: A semiconductor memory device for reading stored data from a selected memory cell in the semiconductor device to a sensing amplifier. An array of memory cells is arranged in a matrix, each memory cell including a MOS transistor. Word lines are organized to select groups of the MOS transistors. A plurality of first bit lines are arrayed in a matrix with the word lines. The word lines and bit lines together select the selected memory cell from the array. Each first bit line is coupled to either the source electrode or drain electrode of a plurality of MOS transistors. There is at least one second bit line. Each second bit line is selectively coupled to at least two corresponding first bit lines. A first bit line selection circuit selectively couples one of the first bit lines to a corresponding second bit line. A first power source line is coupled to the other of the source and drain of the array of the MOS transistors. A second bit line select means selectively couples a second bit line to the sensing amplifier.

    Abstract translation: 一种半导体存储器件，用于将存储的数据从半导体器件中的选定存储单元读取到感测放大器。 存储器单元的阵列被布置成矩阵，每个存储单元包括MOS晶体管。 字线被组织以选择MOS晶体管的组。 多个第一位线以字线排列成矩阵。 字线和位线一起从阵列中选择选定的存储单元。 每个第一位线耦合到多个MOS晶体管的源电极或漏电极。 至少有一个第二位线。 每个第二位线选择性地耦合到至少两个对应的第一位线。 第一位线选择电路将第一位线中的一个选择性地耦合到对应的第二位线。 第一电源线耦合到MOS晶体管阵列的源极和漏极中的另一个。 第二位线选择装置选择性地将第二位线耦合到感测放大器。

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