公开(公告)号：US07271673B2

公开(公告)日：2007-09-18

申请号：US11171860

申请日：2005-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03B5/08

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/0208 ,  H03B2201/0266

Abstract: In accordance with certain described implementations, a voltage controlled oscillator (VCO) includes a VCO coarse tuning bank having multiple coarse tuning bank bits. Each coarse tuning bank bit has an associated bit capacitance. The bit capacitances of the coarse tuning bank bits may be selectively engaged using, for example, a single switching transistor for each coarse tuning bank bit.

Abstract translation: 根据某些描述的实施方案，压控振荡器（VCO）包括具有多个粗调谐存储体位的VCO粗调谐组。 每个粗调谐组位都有相关的位电容。 可以使用例如用于每个粗调谐组位的单个开关晶体管来选择性地接合粗调谐组位的位电容。

公开(公告)号：US07183851B2

公开(公告)日：2007-02-27

申请号：US10883358

申请日：2004-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F2203/45112 ,  H03F2203/45251 ,  H03F2203/45292 ,  H03F2203/45318 ,  H03F2203/45322 ,  H03F2203/45352 ,  H03F2203/45366

Abstract: A method and apparatus to provide a reconfigurable differential dual port current conveyor circuit are described.

Abstract translation: 描述了提供可重新配置的差分双端口电流输送电路的方法和装置。

公开(公告)号：US20050221763A1

公开(公告)日：2005-10-06

申请号：US10812834

申请日：2004-03-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04B17/00

CPC classification number: H04B17/21

Abstract: A method and apparatus are provided to generate calibration signals to multiple stages in a receiver channel. The multiple stages are calibrated using multiple calibration circuits, where a controller controls each calibration circuit. The controller is coupled to the output of the final stage in the receiver channel through a single comparison unit. The output from the single comparison unit is used by the controller to calibrate each of the multiple stages.

Abstract translation: 提供了一种方法和装置，以在接收机通道中的多个级产生校准信号。 多级校准使用多个校准电路，其中控制器控制每个校准电路。 控制器通过单个比较单元耦合到接收机通道中的最后级的输出端。 控制器使用单个比较单元的输出来校准每个多级。

公开(公告)号：US06775345B1

公开(公告)日：2004-08-10

申请号：US09475497

申请日：1999-12-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03D324

CPC classification number: H04L7/0338 ,  H03L7/0814 ,  H04L7/0041

Abstract: An apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay the sampled data by the detected phase difference.

Abstract translation: 一种包括采样电路的装置，用于从本地时钟产生采样时钟，采样时钟采样输入数据和四分之一时钟;相位检测器，用于检测采样数据中的数据转换与本地时钟之间的相位差;以及延迟 线路适于通过检测到的相位差来延迟采样数据。

公开(公告)号：US06639956B1

公开(公告)日：2003-10-28

申请号：US09476978

申请日：1999-12-31

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04L700

CPC classification number: H03K5/135 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0331

Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.

Abstract translation: 一种包括三个采样电路的装置，用于采样输入数据和四分之一时钟。 包括一个时钟生成单元以从本地时钟产生至少三个采样时钟。 三个采样时钟中的每一个被配置为对输入数据和四分之一时钟进行采样。 还包括相位检测器以检测四分之一时钟与本地时钟之间的相位差并产生恢复的四分之一时钟。 还包括延迟线，用于将采样的输入数据和恢复的四分之一时钟延迟检测到的相位差。

公开(公告)号：US06469646B1

公开(公告)日：2002-10-22

申请号：US09867155

申请日：2001-05-29

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03M166

CPC classification number: H03M1/687 ,  H03M1/0673 ,  H03M1/685 ,  H03M1/747 ,  H03M1/785

Abstract: A way of converting digital signals to analog signals is provided. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.

Abstract translation: 提供了一种将数字信号转换为模拟信号的方式。 提供了一种装置，其包括电阻梯形阵列，以将数字输入信号的第一部分转换为第一模拟输出信号。 该装置还包括电流模式阵列，用于将数字输入信号的第二部分转换成第二模拟输出信号。

公开(公告)号：US09548734B1

公开(公告)日：2017-01-17

申请号：US14998090

申请日：2015-12-26

Applicant: Hongjiang Song ,  Yan W. Song ,  Zhiguo Qian ,  Zhichao Zhang

Inventor： Hongjiang Song ,  Yan W. Song ,  Zhiguo Qian ,  Zhichao Zhang

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  H03K19/017545

Abstract: Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

Abstract translation: 实施例通常涉及用于高速I / O的智能阻抗匹配。 在一些实施例中，电路包括阻抗感测块; 有限状态机为驱动器提供阻抗调谐; 和控制块，控制块提供反馈回路来检查和调谐驱动器的阻抗。 阻抗感测块用于对驱动器的输出电压进行采样，以确定驱动器的阻抗是否大于或小于通道的阻抗; 并且有限状态机基于确定驾驶员的阻抗是否大于或小于通道的阻抗来产生信号以减小或增加驾驶员的阻抗。

公开(公告)号：US09184712B2

公开(公告)日：2015-11-10

申请号：US13994672

申请日：2011-12-21

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03F3/45 ,  H04L27/01 ,  H04L25/02 ,  H04L27/00

CPC classification number: H03F3/45645 ,  H03F3/45179 ,  H03F2200/129 ,  H03F2203/45551 ,  H03F2203/45588 ,  H04L25/0276 ,  H04L27/0002 ,  H04L27/01

Abstract: Described herein is a low power high-speed digital receiver. The apparatus of the receiver comprises: a sampling unit operable to sample a differential input signal and to boost input signal gain, the sampling unit to generate a sampled differential signal with boosted input signal gain; and a differential amplifier to amplify the sampled differential signal with boosted input signal gain, the differential amplifier to generate a differential amplified signal.

Abstract translation: 这里描述的是低功率高速数字接收机。 接收机的装置包括：采样单元，可操作以对差分输入信号进行采样并提升输入信号增益，采样单元产生具有升压输入信号增益的采样差分信号; 和差分放大器，用升压的输入信号增益放大采样的差分信号，差分放大器产生差分放大信号。

公开(公告)号：US20150222417A1

公开(公告)日：2015-08-06

申请号：US13994096

申请日：2011-12-21

Applicant: Hongjiang Song ,  Dianbo Le

Inventor： Hongjiang Song ,  Dianbo Le

IPC: H04L7/00 ,  H04L7/10

CPC classification number: H04L7/0079 ,  H03F3/45475 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03G1/0094 ,  H04L7/10

Abstract: Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal.

Abstract translation: 这里描述的是一种低功率静噪电路，其包括时钟产生单元，用于产生时钟信号的第一和第二相位; 采样单元，用于根据时钟信号的第一和第二相采样差分输入信号，采样器产生采样的差分信号; 以及用于放大采样的差分信号的差分放大器。

公开(公告)号：US20150139377A1

公开(公告)日：2015-05-21

申请号：US14608111

申请日：2015-01-28

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H03C3/00 ,  H03C2200/002 ,  H03H11/20 ,  H03H11/22 ,  H03H17/08 ,  H03H2007/0192 ,  H03K17/693 ,  H04L7/0029

Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Abstract translation: 这里描述了对应于低功率数字相位内插器（PI）的装置，方法和系统。 该装置包括：数字混合器单元，用于从一系列输入信号产生相位信号，相位信号具有数字控制的相位; 耦合到数字混频器单元的多相滤波器，通过减少相位信号中的相位误差来产生滤波信号; 以及耦合到多相滤波器的输出缓冲器，以通过缓冲滤波的信号来产生输出信号。 与传统的电流模式PI相比，低功耗数字PI功耗要低，因为数字PI独立于当前模式PI所需的任何偏置电路。