公开(公告)号：US20120292740A1

公开(公告)日：2012-11-22

申请号：US13111563

申请日：2011-05-19

申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0676 ,  H01L27/0802 ,  H01L29/0692 ,  H01L29/8605

摘要： A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode.

摘要翻译： 半导体器件包括半导体衬底，横向半导体二极管，场绝缘结构和多晶硅电阻器。 二极管形成在半导体衬底的表面区域中，并且包括阴极电极和阳极电极。 场绝缘结构设置在阴极和阳极之间。 多晶硅电阻器形成在场绝缘结构之上，并且在阴极和阳极之间。 多晶硅电阻器电连接到阴极电极，并与阳极电极电绝缘。

公开(公告)号：US20090209075A1

公开(公告)日：2009-08-20

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US08921933B2

公开(公告)日：2014-12-30

申请号：US13111018

申请日：2011-05-19

申请人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

发明人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7824 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region.

摘要翻译： 提供半导体结构及其操作方法。 半导体结构包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一沟槽结构和第二栅结构。 第一掺杂区域在衬底中。 第一掺杂区具有第一导电类型。 第二掺杂区域在第一掺杂区域中。 第二掺杂区具有与第一导电类型相反的第二导电类型。 具有第一导电类型的第三掺杂区域在第二掺杂区域中。 第一沟槽结构具有第一栅极结构。 第一栅极结构和第二栅极结构分别位于第二掺杂区域的不同侧。

公开(公告)号：US20140061721A1

公开(公告)日：2014-03-06

申请号：US13596745

申请日：2012-08-28

申请人： Ching-Lin Chan ,  Shyi-Yuan Wu ,  Cheng-Chi Lin ,  Shih-Chin Lien

发明人： Ching-Lin Chan ,  Shyi-Yuan Wu ,  Cheng-Chi Lin ,  Shih-Chin Lien

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/6609 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

摘要： An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention.

摘要翻译： 提供了一种改进的MOS器件，由此p顶层由一系列离散地放置的p型顶部扩散区限定。 本发明还提供了制造本发明的MOS器件的方法。

公开(公告)号：US08482059B2

公开(公告)日：2013-07-09

申请号：US13101486

申请日：2011-05-05

申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0684 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

摘要： A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括第一掺杂阱，第一掺杂电极，第二掺杂电极，掺杂条和掺杂顶区。 掺杂条在第一掺杂电极和第二掺杂电极之间的第一掺杂阱上。 掺杂的条带彼此分离。 掺杂的顶部区域在掺杂的条带上并且在掺杂条带之间的第一掺杂阱上延伸。 第一掺杂阱和掺杂顶区具有第一导电类型。 掺杂的条带具有与第一导电类型相反的第二导电类型。

公开(公告)号：US20120086052A1

公开(公告)日：2012-04-12

申请号：US12899152

申请日：2010-10-06

申请人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

摘要： A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.

摘要翻译： 高压金属氧化物半导体（HVMOS）器件可以包括源极，漏极，位于源极附近的栅极，基本上设置在漏极与栅极和源极区域之间的漂移区域，以及自 屏蔽区域设置在漏极附近。 还提供了相应的方法。

公开(公告)号：US20140015016A1

公开(公告)日：2014-01-16

申请号：US13547549

申请日：2012-07-12

申请人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/0619

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括体，栅极，源极，漏极和体接触区域。 门是大量的。 源极和漏极分别在栅极的相对侧上。 体接触区域仅在与源极相邻的部分的区域中。 体接触区域电连接到本体。

公开(公告)号：US08643072B1

公开(公告)日：2014-02-04

申请号：US13547549

申请日：2012-07-12

申请人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Miao-Chun Chung ,  An-Li Cheng ,  Yin-Fu Huang ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L29/0619

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括体，栅极，源极，漏极和体接触区域。 门是大量的。 源极和漏极分别在栅极的相对侧上。 体接触区域仅在与源极相邻的部分的区域中。 体接触区域电连接到本体。

公开(公告)号：US08829615B2

公开(公告)日：2014-09-09

申请号：US13225349

申请日：2011-09-02

申请人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66492 ,  H01L21/265 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

公开(公告)号：US20130056825A1

公开(公告)日：2013-03-07

申请号：US13225349

申请日：2011-09-02

申请人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/265 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

摘要翻译： 公开了形成半导体器件的半导体器件和方法，其中半导体器件在器件的源极和漏极区域中包括用于改善器件的Ron-sp和BVD特性的附加注入区域。 器件包括形成在器件衬底中分离第一和第二注入区域的沟道区域上的栅电极。 第一植入区域具有第一导电类型，并且第二植入区域具有第二导电类型。 源极扩散区域形成在第一注入区域中，并且漏极扩散区域形成在第二注入区域中。