公开(公告)号：US10083960B2

公开(公告)日：2018-09-25

申请号：US15637170

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H03K17/687 ,  H01L29/49 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L27/0883 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/405 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/7391 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H03K17/687

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US09917181B2

公开(公告)日：2018-03-13

申请号：US15296594

申请日：2016-10-18

Applicant: Infineon Technologies AG

Inventor： Frank Dieter Pfirsch ,  Franz-Josef Niedernostheide ,  Hans-Joachim Schulze ,  Stephan Voss

IPC: H01L29/00 ,  H01L29/739 ,  H01L29/15 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7397 ,  H01L29/8611

Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.

公开(公告)号：US09882038B2

公开(公告)日：2018-01-30

申请号：US15449634

申请日：2017-03-03

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide

IPC: H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L29/739 ,  H01L29/417 ,  H01L29/32 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L21/221 ,  H01L21/263 ,  H01L21/265 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/167 ,  H01L29/32 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

Abstract: A method for forming a bipolar semiconductor switch includes providing a semiconductor body which has a main surface, a back surface arranged opposite to the main surface, and a first semiconductor layer, and reducing a charge carrier life-time in the semiconductor body. The charge carrier life-time is reduced by at least one of indiffusing heavy metal into the first semiconductor layer, implanting protons into the first semiconductor layer and implanting helium nuclei into the first semiconductor layer, so that the charge carrier life-time has, in a vertical direction which is substantially orthogonal to the main surface, a minimum in a lower n-type portion of the first semiconductor layer where a concentration of n-type dopants is substantially close to a maximum.

公开(公告)号：US20180006027A1

公开(公告)日：2018-01-04

申请号：US15635987

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/32

CPC classification number: H01L27/088 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/34 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7397

Abstract: A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure. An active cell field is implemented in the semiconductor body. The active cell field is surrounded by an edge termination zone. A plurality of first cells and a plurality of second cells are provided in the active cell field. Each first cell includes a first mesa, the first mesa including: a first port region and a first channel region. Each second cell includes a second mesa, the second mesa including a second port region. The active cell field is surrounded by a drainage region that is arranged between the active cell field and the edge termination zone.

公开(公告)号：US20170309619A1

公开(公告)日：2017-10-26

申请号：US15492279

申请日：2017-04-20

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Franz-Josef Niedernostheide ,  Alexander Philippou

IPC: H01L27/082 ,  H01L27/02 ,  H01L29/10 ,  H03K17/567

CPC classification number: H01L27/082 ,  H01L25/16 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/78 ,  H03K17/164 ,  H03K17/302 ,  H03K17/567

Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

公开(公告)号：US09627517B2

公开(公告)日：2017-04-18

申请号：US13761213

申请日：2013-02-07

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/32 ,  H01L29/167 ,  H01L21/263 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7393 ,  H01L21/221 ,  H01L21/263 ,  H01L21/265 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/167 ,  H01L29/32 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

Abstract: A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.

公开(公告)号：US20150270347A1

公开(公告)日：2015-09-24

申请号：US14730663

申请日：2015-06-04

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Franz-Josef Niedernostheide ,  Hans-Joachim Schulze

IPC: H01L29/15 ,  H01L29/165 ,  H01L29/739 ,  H01L29/10 ,  H01L29/861 ,  H01L29/74 ,  H01L29/167 ,  H01L29/08

CPC classification number: H01L29/157 ,  H01L29/08 ,  H01L29/10 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/861

Abstract: A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV.

Abstract translation: 半导体器件包括包括第一半导体材料的第一半导体区域和与第一半导体区域邻接的第二半导体区域，第二半导体区域包括不同于第一半导体材料的第二半导体材料。 半导体器件还包括第一半导体区域中的漂移区域和基极区域中的至少一个以及第二半导体区域的发射极区域中的至少一种类型的深度级掺杂剂。 至少一种类型的深层掺杂剂具有至少100meV的价带或导带的距离。

公开(公告)号：US11876509B1

公开(公告)日：2024-01-16

申请号：US17875876

申请日：2022-07-28

Applicant: Infineon Technologies AG

Inventor： Guang Zeng ,  Franz-Josef Niedernostheide ,  Mark-Matthias Bakran ,  Zheming Li

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03K17/166 ,  H03K17/168 ,  H03K17/687 ,  H03K2217/0027

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

公开(公告)号：US11309410B2

公开(公告)日：2022-04-19

申请号：US16890822

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

公开(公告)号：US11276772B2

公开(公告)日：2022-03-15

申请号：US16864608

申请日：2020-05-01

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.