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    Serializer/deserializer apparatus with loopback configuration and methods thereof
    31.
    发明授权
    Serializer/deserializer apparatus with loopback configuration and methods thereof 有权
    具有环回配置的串行器/解串器设备及其方法

    公开(公告)号：US08731031B1

    公开(公告)日：2014-05-20

    申请号：US13802620

    申请日：2013-03-13

    Applicant: Inphi Corporation

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04B1/38

    CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

    Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer is directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

    Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

    Variable gain amplifiers for communication systems
    32.
    发明授权
    Variable gain amplifiers for communication systems 有权

    公开(公告)号：US10763810B2

    公开(公告)日：2020-09-01

    申请号：US16810651

    申请日：2020-03-05

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03G3/22 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00 ,  H03G3/00 ,  H03G7/06

    Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

    Compact high speed duty cycle corrector
    33.
    发明授权
    Compact high speed duty cycle corrector 有权

    公开(公告)号：US10333527B2

    公开(公告)日：2019-06-25

    申请号：US16154522

    申请日：2018-10-08

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H04L27/01 ,  H03L7/08 ,  H03K5/156 ,  H03G3/20

    Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    Differential circuits with constant GM bias
    35.
    发明授权
    Differential circuits with constant GM bias 有权

    公开(公告)号：US10103698B2

    公开(公告)日：2018-10-16

    申请号：US15633521

    申请日：2017-06-26

    Applicant: INPHI CORPORATION

    Inventor： Rajasekhar Nagulapalli ,  Simon Forey ,  Parmanand Mishra

    IPC: H03F3/45 ,  H03F1/34

    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.

    Continuous time linear equalization for current-mode logic with transformer
    36.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权

    公开(公告)号：US09853842B2

    公开(公告)日：2017-12-26

    申请号：US15359338

    申请日：2016-11-22

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H04L25/03 ,  H03K19/094 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Offset correction for sense amplifier
    40.
    发明授权
    Offset correction for sense amplifier 有权

    公开(公告)号：US09621176B2

    公开(公告)日：2017-04-11

    申请号：US15277076

    申请日：2016-09-27

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Simon Forey

    IPC: H03M1/10 ,  H04L25/03 ,  H03M1/66

    CPC classification number: H03M1/1023 ,  H03M1/66 ,  H04L25/03057 ,  H04L25/03878

    Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

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