公开(公告)号：US10579269B2

公开(公告)日：2020-03-03

申请号：US16105363

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/00 ,  G06F3/06

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US10438656B2

公开(公告)日：2019-10-08

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Bharat M. Pathak ,  Binh N. Ngo ,  Naveen Vittal Prabhu ,  Karthikeyan Ramamurthi ,  Pranav Kalavade

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C8/08 ,  G11C16/32

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

公开(公告)号：US10276252B2

公开(公告)日：2019-04-30

申请号：US15838202

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/22 ,  G11C16/10 ,  G11C11/56

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

公开(公告)号：US10268407B1

公开(公告)日：2019-04-23

申请号：US15721351

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Naveen Vittal Prabhu ,  Yu Du ,  Purval Shyam Sule

IPC: G11C16/26 ,  G06F3/06

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

公开(公告)号：US10229057B2

公开(公告)日：2019-03-12

申请号：US15282036

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Bharat M. Pathak

IPC: G06F12/02 ,  G06F12/06 ,  G11C16/20 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

公开(公告)号：US20180095689A1

公开(公告)日：2018-04-05

申请号：US15282036

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Bharat M. Pathak

IPC: G06F3/06 ,  G11C16/20 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G06F12/06

CPC classification number: G06F12/0646 ,  G06F12/0246 ,  G06F2212/1008 ,  G06F2212/2022 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/3459

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

公开(公告)号：US09471488B2

公开(公告)日：2016-10-18

申请号：US14961424

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G06F12/02 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/14 ,  G11C5/14 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

公开(公告)号：US09208888B1

公开(公告)日：2015-12-08

申请号：US14318572

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Charan Srinivasan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30 ,  G11C16/14 ,  G11C5/14 ,  G11C11/16 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了提高闪存系统中部分写入的存储块的可靠性和/或性能的方法和装置。 在一些实施例中，存储设备存储对应于在非易失性存储器的部分编程的存储器块上执行的部分写入操作的信息。 至少部分地基于所存储的信息，存储器控制器逻辑然后在对非易失性存储器的读取或写入操作期间使非常易失性存储器的部分的减小的电压电平和/或偏移值应用于非易失性存储器。 还公开并要求保护其他实施例。