公开(公告)号：US11276618B2

公开(公告)日：2022-03-15

申请号：US15967122

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Andrew J. Brown

IPC: H01L23/14 ,  B32B27/12 ,  B32B5/02 ,  B32B5/26 ,  B32B27/38 ,  B32B27/36 ,  H01L23/538 ,  H01L21/48 ,  H05K1/03 ,  H01L23/498 ,  H05K5/00 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US11189409B2

公开(公告)日：2021-11-30

申请号：US15856547

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L21/48 ,  H01F1/20 ,  H01L23/498 ,  H01F41/02 ,  H05K1/18 ,  H01F1/37 ,  H01F1/28 ,  H01L23/00

Abstract: An inductor may be fabricated comprising a magnetic material layer and an electrically conductive via or trace extending through the magnetic material layer, wherein the magnetic material layer comprises dielectric magnetic filler particles within a carrier material. Further embodiments may include incorporating the inductor of the present description into an electronic substrate and may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US20190355642A1

公开(公告)日：2019-11-21

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/367 ,  H01L23/538 ,  H01L21/56

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US20190206780A1

公开(公告)日：2019-07-04

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US20190198436A1

公开(公告)日：2019-06-27

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01L23/49838 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F2027/2809 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US20190198228A1

公开(公告)日：2019-06-27

申请号：US15854460

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Lauren A. Link ,  Andrew J. Brown

IPC: H01F27/28 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01F27/2828 ,  H01L21/76802 ,  H01L23/5227 ,  H01L28/10

Abstract: An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.