公开(公告)号：US12087836B2

公开(公告)日：2024-09-10

申请号：US18382339

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC: H01L29/423 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20240290651A1

公开(公告)日：2024-08-29

申请号：US18655567

申请日：2024-05-06

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Manish Chandhok ,  Gurpreet Singh

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7681 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2221/1036

Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

公开(公告)号：US11664305B2

公开(公告)日：2023-05-30

申请号：US16455662

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Kevin Lai Lin ,  Manish Chandhok ,  Miriam Reshotko ,  Christopher Jezewski ,  Eungnak Han ,  Gurpreet Singh ,  Sarah Atanasov ,  Ian A. Young

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/5226

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

公开(公告)号：US20230085997A1

公开(公告)日：2023-03-23

申请号：US17483439

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Yi Yang ,  Eungnak Han ,  Suddhasattwa Nad ,  Marcel Wall

IPC: H05K3/38

Abstract: Methods and apparatus to improve adhesion between metals and dielectrics in circuit devices are disclosed. An apparatus includes a metal layer, a dielectric layer adjacent the metal layer, and a polymeric bonding layer at an interface between the metal layer and the dielectric layer. A polymer molecule in the polymeric bonding layer including an R1 group, an R2 group, and a polymer chain extending between the R1 group and the R2 group. The R1 group is different than the R2 group. The polymeric bonding layer is bonded to the metal layer via the R1 group. The polymeric bonding layer is bonded to the dielectric layer via the R2 group.

公开(公告)号：US11605623B2

公开(公告)日：2023-03-14

申请号：US16457699

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Eungnak Han ,  Paul A. Nyhus ,  Florian Gstrein ,  Richard E. Schenker

IPC: H01L27/02 ,  C08L33/12 ,  C08L25/06 ,  C08L53/00

Abstract: An integrated circuit structure includes an active region containing more active semiconductor devices, wherein the active region comprises a first grating of metal and dielectric materials with only vertically aligned structures thereon. A transition region containing inactive structures is adjacent to the active region, wherein the transition region comprises a second grating of metal and dielectric materials having at least one of vertical aligned structures and vertical random structures thereon. Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon.

公开(公告)号：US20220102148A1

公开(公告)日：2022-03-31

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US10892184B2

公开(公告)日：2021-01-12

申请号：US16317015

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Kevin L. Lin ,  James M. Blackwell ,  Rami Hourani ,  Eungnak Han

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US09530733B2

公开(公告)日：2016-12-27

申请号：US14909736

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  James M. Blackwell ,  Scott B. Clendenning ,  Florian Gstrein ,  Eungnak Han ,  Grant M. Kloster ,  Jeanette M. Roberts ,  Patricio E. Romero ,  Rami Hourani

IPC: H01L23/58 ,  H01L23/528 ,  H01L21/32 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US09418888B2

公开(公告)日：2016-08-16

申请号：US14778562

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Rami Hourani ,  Eungnak Han ,  James M. Blackwell

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.