公开(公告)号：US09948299B2

公开(公告)日：2018-04-17

申请号：US15462664

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  Alexey Kostinsky

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US09865326B2

公开(公告)日：2018-01-09

申请号：US15363399

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

IPC: G06F13/10 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US09704544B2

公开(公告)日：2017-07-11

申请号：US15360675

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

IPC: G06F12/00 ,  G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

公开(公告)号：US09552164B2

公开(公告)日：2017-01-24

申请号：US14440066

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G11C5/14 ,  G11C29/02

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收到的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器件。

公开(公告)号：US20160342539A1

公开(公告)日：2016-11-24

申请号：US14865718

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G06F13/16

CPC classification number: G06F13/16 ,  G06F13/1684

Abstract: A memory device includes at least two independent interface paths, an interface path including multiple memory banks. The memory device can selectively operate in a bank mode or a bank group mode. In bank mode, banks are operated as logical banks, where separate physical banks from different interface paths operate in parallel. When a logic bank is accessed, all physical banks belonging to the logical bank are accessed in parallel across the interface paths. In bank group mode, banks are operated independently, but accessed in bank groups. A separate interface path is operated as an independent bank group, and a bank is individually accessed in its bank group. In bank group mode, back to back access to separate bank groups is possible without resulting in access delay.

Abstract translation: 存储器件包括至少两个独立的接口路径，包括多个存储体的接口路径。 存储器件可以选择性地以存储体模式或存储体组模式操作。 在银行模式下，银行作为逻辑银行运作，其中不同接口路径的独立物理存储库并行运行。 当访问逻辑组时，属于逻辑组的所有物理库在接口路径上并行访问。 在银行集团模式下，银行独立经营，但以银行集团存取。 单独的接口路径作为独立的银行组操作，银行在其银行组中单独访问。 在银行组模式下，背靠背访问分离的银行组是可能的，而不会导致访问延迟。

公开(公告)号：US09436632B2

公开(公告)日：2016-09-06

申请号：US14560976

申请日：2014-12-04

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

IPC: G06F13/28 ,  G06F11/10 ,  G06F11/16 ,  G11C29/44 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

公开(公告)号：US12265723B2

公开(公告)日：2025-04-01

申请号：US17485343

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Ru Yin Ng ,  Saravanan Sethuraman ,  Kuljit S. Bains

IPC: G06F3/06

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

公开(公告)号：US12235720B2

公开(公告)日：2025-02-25

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Hsing-Min Chen ,  Wei P. Chen ,  Wei Wu ,  Jing Ling ,  Kuljit S. Bains ,  Kjersten E. Criss ,  Deep K. Buch ,  Theodros Yigzaw ,  John G. Holm ,  Andrew M. Rudoff ,  Vaibhav Singh ,  Sreenivas Mandava

IPC: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US12181966B2

公开(公告)日：2024-12-31

申请号：US17225777

申请日：2021-04-08

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Narasimha Lanka

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

公开(公告)号：US11210167B2

公开(公告)日：2021-12-28

申请号：US16722969

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/16

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The ECC for an N/2-bit channel is simpler than the ECC for N bits, and thus, each N/2-bit portion can be separately correctable when treated as two N/2-bit portions. The memory device can include an additional hardware for the application of ECC to the channel as two sub-channels. For example, the memory device can include an additional subarray to store ECC bits for the internal ECC to enable the application of ECC to two sub-channels of the N-bit channel. The memory device can include an additional driver to access the additional subarray when applied.